1
Koichi Yamada, Gary N Hammond: Method and apparatus for preloading different default address translation attributes. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 29, 1999: US05918251 (74 worldwide citation)

A method and apparatus for streamlining the installation of virtual to physical address translations into a translation unit. According to one aspect of the invention, an apparatus for use in a computer system is provided that generally includes a translation unit, a default attribute storage area, ...


2
Hideo Ishizaka, Yoshio Saito, Yukihide Miyata, Takashi Koizumi, Yasuhiro Asai, Shinichi Nakama, Tadashi Uekusa, Shinichi Matsuda, Koichi Yamada: Long-test-film cassette for biochemical analysis, and system for loading the same. Fuji Photo Film, Sughrue Mion Zinn Macpeak & Seas, December 31, 1991: US05077010 (65 worldwide citation)

A long-test-film cassette for biochemical analysis comprises an unused film cassette part accommodating an unused long test film for biochemical analysis, and a used film cassette part for accommodating the long test film which has been pulled out of the unused film cassette part and used for bioche ...


3
William R Bryg, Stephen G Burger, Gary N Hammond, James O Hays, Jerome C Huck, Jonathan K Ross, Sunil Saxena, Koichi Yamada: Method and apparatus for calculating a page table index from a virtual address. Institute for the Development of Emerging Architectures L L C, David A Plettue, May 21, 2002: US06393544 (60 worldwide citation)

A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, ...


4
William R Bryg, Stephen G Burger, James O Hays, John M Kessenich, Jonathan K Ross, Gary N Hammond, Sunil Saxena, Koichi Yamada: Apparatus and method for a virtual hashed page table. Hewlett Packard Co, August 6, 2002: US06430670 (60 worldwide citation)

The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translat ...


5
Suresh Marisetty, Andrew J Fish, Koichi Yamada, Scott D Brenden, James B Crossland, Shivnandan Kaushik, Mohan J Kumar, Jose A Vargas: OS and firmware coordinated error handling using transparent firmware intercept and firmware services. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 9, 2009: US07546487 (55 worldwide citation)

Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning plat ...


6
Gary N Hammond, Koichi Yamada, Stephen G Burger, James O Hays, Jonathan K Ross, William R Bryg: Software and hardware-managed translation lookaside buffer. Intel Corporation, Arnold White & Durkee, August 17, 1999: US05940872 (50 worldwide citation)

A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage location in the TLB is both hardware-managed and software-managed. The TLB also includes a second storage ...


7
Koichi Yamada, Gary N Hammond, Jim Hays, Jonathan Kent Ross, Stephen Burger, William R Bryg: Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. Institute for the Development of Emerging Architecture L L C, Blakely Sokoloff Taylor & Zafman, July 11, 2000: US06088780 (44 worldwide citation)

A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is prov ...


8
Yasuo Kasai, Koichi Yamada, Teruo Sakuma, Masahiro Koguchi: Making process of a die for stamping out patterns. Fujikura Cable Works, Hill Van Santen Steadman & Simpson, April 1, 1986: US04579022 (36 worldwide citation)

The invention provides a novel method for manufacturing a knife-edge die for stamping out a metal foil on an insulating base plate such as in the preparation of an electronic circuit board by a technique of photoetching. The method comprises a line pattern of a photoresist film on the die face corre ...


9
Gary N Hammond, Koichi Yamada: Method and apparatus for performing process switching in multiprocessor computer systems. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 27, 2001: US06209085 (34 worldwide citation)

A method and apparatus for reducing the amount of data copied during process switches. A method for reducing the amount of data copied during process switches is provided. In response to a processor performing a process switch to a process, a first write indication corresponding to the process is st ...


10
Koichi Yamada, Tadanori Hashimoto, Kazuo Horinouchi: Electrodes for aluminum reduction cells. Sumitomo Aluminum Smelting Company, Stevens Davis Miller & Mosher, November 6, 1979: US04173518 (30 worldwide citation)

An electrode for aluminum reduction cells wherein an electrode base, at least in that portion which is brought into contact with a molten salt bath, is coated with a composition comprising at least 50% by weight of electronic conductive oxide ceramics, or said portion of the electrode is made of sai ...