1
Toru Watabe, Yasutomo Sakurai, Takumi Kishino, Yoshio Hirose, Koichi Odahara, Kazuhiro Nonomura, Takumi Takeno, Shinya Katoh, Takato Noda: Information processing system. Fujitsu, Staas & Halsey, November 10, 1998: US05835697 (23 worldwide citation)

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processo ...


2
Toru Watabe, Yasutomo Sakurai, Takumi Kishino, Yoshio Hirose, Koichi Odahara, Kazuhiro Nonomura, Takumi Takeno, Shinya Katoh, Takato Noda: Information processing system. Fujitsu, Staas & Halsey, June 6, 2000: US06073249 (15 worldwide citation)

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processo ...


3
Masatoshi Michizono, Toshiyuki Muta, Koichi Odahara, Yasutomo Sakurai, Shinya Katoh: Arbitration circuit for arbitrating requests from multiple processors. Fujitsu, Staas & Halsey, February 22, 2000: US06029219 (11 worldwide citation)

A round robin arbitration circuit arbitrating N requests has a register storing one of N values, a priority encoder selecting one of N priority patterns according to the value in the register and assigning priorities to the requests based on the selected priority pattern, thereby conducting arbitrat ...


4
Kiyoshi Sudo, Yasutomo Sakurai, Koichi Odahara, Kenji Hoshi, Hideharu Kanaya: Clock control circuit for suppressing clock pulses. Fujitsu, Welsh & Katz, March 9, 1993: US05192914 (7 worldwide citation)

In a clock control circuit for suppressing a clock pulse in a plurality of devices which operate in synchronization with each other, the clock control circuit detects first and second clock suppress conditions, generates a first clock suppress signal in all the devices based on the detection of the ...


5
Kiyoshi Sudo, Yasutomo Sakurai, Koichi Odahara, Kenji Hoshi, Hideharu Kanaya: Access processing system in information processor. Fujitsu, Staas & Halsey, July 5, 1994: US05327539 (3 worldwide citation)

In an access processing system in an information processor, the information processor includes: an access device (10, 11) for generating an access request signal; an accessed device (13) provided with a memory means (30) that is accessed by the access device (10, 11); and an address bus (14) that ha ...


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Takayuki Kinoshita, Junji Ichimiya, Shintaro Itozawa, Koichi Odahara: Data processing system, data processing apparatus, and data processing method. Fujitsu, Staas & Halsey, February 21, 2008: US20080043734-A1

When a new data relaying device that has yet to have configuration information set therein is incorporated, the configuration information of an existing data relaying device is copied to the new data relaying device.