1
Kimura Kozo, Kiyohara Tokuzo, Yoshioka Kousuke: Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream. Matsushita Electric, March 4, 1998: EP0827071-A2 (36 worldwide citation)

A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for executing instructions; a plurality of instruction decode units, corresponding to the multiple instruction streams on a one-to-one basis, for r ...


2
Tanaka Takaharu, Maenobu Kyoshi, Yoshioka Kosuke, Hirai Makoto, Kiyohara Tokuzo: Processor capable of efficiently executing many asynchronous event tasks. Matsushita Electric, September 9, 1998: EP0863462-A2 (33 worldwide citation)

The counter 52 is set with an initial value of "1" and is a counter with a maximum value of "4". This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1, 2,3,4. This clock signal ...


3
Kurata Kazuji, Tanaka Tetsuya, Fujii Shigeki, Higaki Nobuo, Kiyohara Tokuzo, Kimura Kozo, Nishida Hideshi, Sugimura Toshio, Kadota Hiroshi, Furukawa Kazuya, Hayashi Kunihiko: Processor and program executing method. Matsushita Electric, September 26, 2003: JP2003-271399 (23 worldwide citation)

PROBLEM TO BE SOLVED: To provide a processor capable of efficiently executing a plurality of programs even at the time of executing those processors in pseudo parallel by one processor.SOLUTION: This processor for executing a plurality of programs by using a plurality of register value groups stored ...


4
Kiyohara Tokuzo, Deguchi Masashi: Loosely coupled pipeline processor.. Matsushita Electric, June 29, 1988: EP0272705-A2 (17 worldwide citation)

A central processing unit includes an instruction decoder (1), an operand address computation unit (2), an operand pre-fetch unit (3), a control information buffer (5), an arithmetic unit (4), an instruction fetch unit (6), a chip bus (7), and a bus controller (8). A process relating to the fetch of ...


5
Morishita Hiroyuki, Hashimoto Takashi, Kiyohara Tokuzo: Processor. Matsushita Electric, March 6, 2008: JP2008-052750 (7 worldwide citation)

PROBLEM TO BE SOLVED: To provide a processor which is flexible and high in performance while suppressing a circuit scale.SOLUTION: The processor, which cyclically executes a plurality of threads with each thread executed for a respective time assigned thereto, has a reconfigurable integrated circuit ...


6
Kataoka Tomonori, Nishida Hideshi, Kimura Kozo, Higaki Nobuo, Kiyohara Tokuzo: Signal-processor and electronic equipment using it. Matsushita Electric, March 17, 2005: JP2005-070938 (6 worldwide citation)

PROBLEM TO BE SOLVED: To provide a signal-processor capable of performing a high-performance and high-efficiency image processing for an image processing requesting a large data processing amount such as encoding/decoding processing of MPEG-4 AVC, and electronic equipment using the apparatus.SOLUTIO ...


7
Kataoka Tomonori, Nishida Hideshi, Kimura Kouzou, Higaki Nobuo, Kiyohara Tokuzo: Digital video signal processing apparatus. Matsushita Electric, February 23, 2005: EP1509044-A2 (6 worldwide citation)

A signal-processing apparatus comprises an instruction-parallel processor (100), a first data-parallel processor (101), a second data-parallel processor (102), and a motion detection unit (103), a de-blocking filtering unit (104) and a variable-length coding/decoding unit (105) which are dedicated h ...


8
Yoshioka Kosuke, Kiyohara Tokuzo, Mochida Tetsuji, Kimura Kozo, Ochiai Toshiyuki: Data processing apparatus with buffering between buses. Matsushita Electric, January 17, 2001: EP1069512-A2 (5 worldwide citation)

The local buffers 13-15 connected to the buses 10-12 input and output data in a manner that cancels out the difference between the data transfer speeds of the bus 1 and the buses 10-12, where the data transfer speed of a bus changes in proportion to the bit width of the bus. The data transfer rates ...


9
Yoshioka Kosuke, Hirai Makoto, Kiyohara Tokuzo, Kimura Kozo: Image decoder and image memory overcoming various kinds of delaying factors caused by hardware specifications specific to image memory by improving storing system and reading-out system. Matsushita Electric, August 19, 1998: EP0859524-A1 (4 worldwide citation)

An image memory stores a one-screen image by dividing the one-screen image into a plurality of image blocks which are each m pixels wide by n pixels high. The image memory has an array-like storage region storing s*t first chrominance components that compose one image block and s*t second chrominanc ...


10
Nakanishi Ryuta, Okabayashi Hazuki, Tanaka Tetsuya, Kiyohara Tokuzo: Cache memory and control method thereof. Matsushita Electric, December 6, 2006: EP1729220-A1 (4 worldwide citation)

The cache memory in the present invention includes a prediction unit 39 which predicts, based on the progress of the memory access outputted from the memory, a line address which should be prefetched next. The prediction unit 39 includes: a prefetch unit 414 which prefetches data of the predicted li ...