1
Belgacem Haba Belgacem (Bel) Haba
Kishor Desai, Belgacem Haba, Wael Zohni: Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts. Tessera, Lerner David Littenberg Krumholz & Mentlik, February 19, 2013: US08378478 (43 worldwide citation)

The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelec ...


2
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Ilyas Mohammed, Ellis Chau, Sang Il Lee, Kishor Desai: No flow underfill. Tessera, Lerner David Littenberg Krumholz & Mentlik, April 15, 2014: US08697492 (16 worldwide citation)

A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and oth ...


3
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Kishor Desai: Low CTE interposer. Invensas Corporation, Lerner David Littenberg Krumholz & Mentlik, July 15, 2014: US08780576 (3 worldwide citation)

An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support porti ...


4
Belgacem Haba Belgacem (Bel) Haba
Kishor Desai, Belgacem Haba, Wael Zohni: Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts. Tessera Research, May 24, 2012: US20120126389-A1

The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelec ...


5
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Ilyas Mohammed, Ellis Chau, Sang Il Lee, Kishor Desai: No flow underfill. Tessera Research, May 3, 2012: US20120104595-A1

A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and oth ...


6
Kumar Nagarajan, Kishor Desai: Flip chip ball grid array package with laminated substrate. LSI Logic Corporation, October 17, 2000: US06133064 (47 worldwide citation)

Methods and apparatus pertaining to flip chip ball grid array packages are disclosed. A substrate comprises a base layer with a dielectric laminated thereon such that a cavity in the dielectric exposes the base layer. A die is then mounted to the exposed portion of the base layer. Preferably, an upp ...


7
Sarathy Rajagopalan, Kishor Desai: Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die. LSI Logic Corporation, Westman Champlin & Kelly, February 11, 2003: US06518161 (10 worldwide citation)

A method for creating a die that has some bond pads that are compatible with wire bonding and others that are compatible with solder bonding. A layer of copper is disposed over aluminum bond pads and selectively removed from those bond pads that are desired to be compatible with wire bonding.


8
Sarathy Rajagopalan, Kishor Desai, Maniam Alagaratnam: Dual chip in package with a wire bonded die mounted to a substrate. LSI Logic Corporation, Westman Champlin & Kelly, July 1, 2003: US06586825 (7 worldwide citation)

A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. The bott ...


9
Sarathy Rajagopalan, Kishor Desai, John P McCormick, Maniam Alagaratnam: Multi chip module assembly. LSI Logic Corporation, Luedeka Neely Graham P C, May 9, 2006: US07041516 (4 worldwide citation)

A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second int ...


10
Charles G Woychik, Kishor Desai, Ilyas Mohammed, Terrence Caskey: Low-stress TSV design using conductive particles. Tessera, Lerner David Littenberg Krumholz & Mentlik, May 13, 2014: US08723049 (3 worldwide citation)

A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can in ...