1
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, Michael E Whitham, Eugene I Shkurko, Mark F Chadurjian, November 19, 2002: US06483156 (132 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


2
Jeffrey P Gambino, Kirk D Peterson: Method and structure to prevent circuit network charging during fabrication of integrated circuits. International Business Machines Corporation, Schmeiser Olsen & Watts, William D Sabo, June 19, 2007: US07232711 (27 worldwide citation)

An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of th ...


3
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, William D Sabo, Whitham Curtis & Christofferson P C, December 9, 2003: US06660596 (23 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


4
Eric Soenen, James E Nave, Kirk D Peterson, Andrew J Cringean, James R C Craig: Analog to digital video converter. Texas Instruments Incorporated, Robby T Holland, Carl H Hoel, Richard L Donaldson, February 23, 1999: US05874909 (22 worldwide citation)

An integrated analog to digital interface subsystem for imaging applications includes digital global and digital pixel by pixel offset correction and scaling. The integrated interface 2 includes 3 DAC's 2c1-2c3 that are used to do a rough offset cancellation on the three analog input signals (RGB) i ...


5
Thomas G Ference, William F Landers, Michael J MacDonald, Walter E Mlynko, Mark P Murray, Kirk D Peterson: Combined chemical mechanical polishing and reactive ion etching process. International Business Machines, Howard J Walter Jr Esq, Ratner & Prestia, April 24, 2001: US06221775 (21 worldwide citation)

A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemica ...


6
John J Ellis Monaghan, Kirk D Peterson, Jeffrey S Zimmerman: Halo implant in semiconductor structures. International Business Machines Corporation, Schmeiser Olsen & Watts, William D Sabo, September 27, 2005: US06949796 (18 worldwide citation)

A halo implant method for forming halo regions of at least first and second transistors formed on a same semiconductor substrate. The first transistor comprises a first gate region disposed between first and second semiconductor regions. The second transistor comprises a second gate region disposed ...


7
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Charles W Koburger III, Kirk D Peterson: Sidewall image transfer (SIT) technologies. International Business Machines Corporation, Schmeiser Olsen & Watts, William D Sabo, September 4, 2007: US07265013 (17 worldwide citation)

A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed o ...


8
Marc W Cantell, Kenneth Giewont, Jerome B Lasky, Kirk D Peterson: Plasma etch pre-silicide clean. International Business Machines Corporation, John J Tomaszewski, William D Sabo, DeLio & Peterson, July 3, 2001: US06255179 (9 worldwide citation)

A method of preparing silicon semiconductor surfaces prior to metal silicide formation. In particular, it teaches a method of treating about 10 to about 200 Å of a surface of the silicon with a plasma source after activating the source and drain regions, prior to an HF etch and deposition of a ...


9
Kirk D Peterson, Dana Dudley, Kevin N Sweetser: Focal plane array integrated circuit with individual pixel signal processing. Texas Instruments Incorporated, Gerald E Laws, C Alan McClure, James C Kesterson, March 17, 1998: US05729285 (9 worldwide citation)

This is a monolithic infrared detector readout circuit for a capacitive sensing element 111 wherein a high gain preamplifier 115 is biased by a large bias element 113, e.g. on the order of 10.sup.12 ohms. The output of the preamplifier 115 is band-limited by a low pass single-pole filter 117 having ...


10
Dana Dudley, Kirk D Peterson, Charles M Hanson: Uncooled infrared detector readout monolithic integrated circuit with individual pixel signal processing. Texas Instruments Incorporated, Richard L Donaldson, Rene E Grossman, September 1, 1992: US05144133 (9 worldwide citation)

A monolithic infrared detector readout circuit for a capacitive detection element wherein a high gain preamplifier is biased by a large amplifier feedback resistance, on the order of 10.sup.12 ohms. The output of the preamplifier is bandlimited by a low pass single-pole filter having a high value re ...