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Wendell P Noble, Leonard Forbes, Kie Y Ahn: Memory cell having a vertical transistor with buried source/drain and dual gates. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, November 21, 2000: US06150687 (256 worldwide citation)

An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of th ...


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Kie Y Ahn, Leonard Forbes, Eugene H Cloud: Structure and method for a high-performance electronic packaging assembly. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, May 27, 2003: US06570248 (235 worldwide citation)

An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can c ...


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Kie Y Ahn, Leonard Forbes: Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, July 26, 2005: US06921702 (209 worldwide citation)

A dielectric film containing HfO2/ZrO2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer deposition of HfO2 using a HfI4 precursor fo ...


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Wendell P Noble, Leonard Forbes, Kie Y Ahn: Four F.sup.2 folded bit line DRAM cell structure having buried bit and word lines. Micro Technology, Schwegman Lundberg Woessner & Kluth P A, June 6, 2000: US06072209 (205 worldwide citation)

A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transi ...


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Leonard Forbes, Wendell P Noble, Kie Y Ahn: Method of making memory cell with vertical transistor and buried word and body lines. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, June 1, 1999: US05909618 (191 worldwide citation)

An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provi ...


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Kie Y Ahn, Leonard Forbes: Atomic layer-deposited LaAlO3 films for gate dielectrics. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, May 16, 2006: US07045430 (186 worldwide citation)

A dielectric film containing LaAlO3 and method of fabricating a dielectric film contained LaAlO3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO2. The LaAlO3 gate dielectrics formed are thermodynamically stable such that these gate dielectrics ...


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Kie Y Ahn, Leonard Forbes, Eugene H Cloud: Structure and method for a high performance electronic packaging assembly. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, August 28, 2001: US06281042 (185 worldwide citation)

An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can c ...


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Leonard Forbes, Kie Y Ahn: Flash memory with ultra thin vertical body transistors. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, July 23, 2002: US06424001 (184 worldwide citation)

Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from a semiconductor substrate. The pillar includ ...


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Kie Y Ahn, Leonard Forbes: Formation of metal oxide gate dielectric. Micron Technology, Mueting Raasch & Gebhardt P A, December 17, 2002: US06495436 (181 worldwide citation)

Formation of a gate dielectric includes forming a metal oxide on at least a portion of the surface of the substrate assembly by electron beam evaporation. An ion beam is generated using an inert gas to provide inert gas ions for compacting the metal oxide during formation thereof.



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