An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of th ...
An ultra-thin gate oxide layer of hafnium oxide (HfO
An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can c ...
A dielectric film containing HfO2/ZrO2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer deposition of HfO2 using a HfI4 precursor fo ...
A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transi ...
A dielectric film containing LaAlO3 and method of fabricating a dielectric film contained LaAlO3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO2. The LaAlO3 gate dielectrics formed are thermodynamically stable such that these gate dielectrics ...
An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provi ...
An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can c ...
Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from a semiconductor substrate. The pillar includ ...
Formation of a gate dielectric includes forming a metal oxide on at least a portion of the surface of the substrate assembly by electron beam evaporation. An ion beam is generated using an inert gas to provide inert gas ions for compacting the metal oxide during formation thereof.
