1
Khue Duong: Tile-based modular routing resources for high density programmable logic device. Xilinx, Anthony C Wagner Murabito & Hao Murabito, Jeanette S Harms, March 9, 1999: US05880598 (232 worldwide citation)

Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are p ...


2
Stephen M Trimberger, Khue Duong: Multi-buffered configurable logic block output lines in a field programmable gate array. Xilinx, Jeanette S Harms, Anthony C Murabito, September 29, 1998: US05815004 (133 worldwide citation)

A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drive ...


3
Khue Duong, Stephen M Trimberger: Interconnect lines including tri-directional buffer circuits. Xilinx, Jeanette S Harms, Wagner Murabito & Hao, August 12, 1997: US05656950 (88 worldwide citation)

A metal interconnect line for conducting a first signal from a first line segment of a field programmable gate array to a second line segment. The metal interconnect line substantially spans across the width of the field programmable gate array and has at least one bi-directional buffer that separat ...


4
Khue Duong, Stephen M Trimberger, Bernard J New: Fast carry-out scheme in a field programmable gate array. Xilinx, Jeanette S Harms, Wagner Murabito & Hao, October 7, 1997: US05675262 (71 worldwide citation)

A fast carry-out scheme in a field programmable logic array. The configurable logic blocks (CLBs) are arranged in columns. The carry-out signals are routed from the bottom CLB of a column to the top CLB of that column. The carry-out from the top-most CLB is then multiplexed onto a clock line that is ...


5
Stephen M Trimberger, Khue Duong: Periphery input/output interconnect structure. Xilinx, Jeanette S Harms, Wagner Murabito & Hao, June 24, 1997: US05642058 (63 worldwide citation)

A mechanism is provided for allowing input/output signal routing along the periphery of a programmable integrated circuit (IC) so that uniform circuit usage across the programmable integrated circuit is allowed in conjunction with predetermined pin assignments. The mechanism includes a plurality of ...


6
Stephen M Trimberger, Khue Duong, Robert O Conn Jr: Output multiplexer circuit for input/output block. Xilinx, Jeanette S Harms, Anthony C Murabito Wagner Murabito & Hao, September 22, 1998: US05811985 (55 worldwide citation)

A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also ...


7
Stephen M Trimberger, Khue Duong, Robert O Conn Jr: Output multiplexer within input/output circuit for time multiplexing and high speed logic. Xilinx, Jeanette S Harms, Anthony C Murabito, January 14, 1997: US05594367 (37 worldwide citation)

A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also ...


8
Khue Duong, Stephen M Trimberger, Alok Mehrotra: Programmable single buffered six pass transistor configuration. Xilinx, Wagner Murabito & Hao, February 4, 1997: US05600264 (35 worldwide citation)

A programmable single buffered six transistor switch box is provided. A six transistor switch box acts as a programmable junction between four intersecting lines. The switch box allows any two of the lines to be programmably interconnected to form a signal channel. Alternatively, two sets of the fou ...


9
Ross H Freeman deceased, Khue Duong, Hung Cheng Hsieh, Charles R Erickson, William S Carter: Programmable connector for programmable logic device. Xilinx, Edel M Young, Bradley A Greenwald, Alan H MacPherson, August 18, 1992: US05140193 (33 worldwide citation)

A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interco ...


10
Sheau Suey Li, Randy T Ong, Samuel Broydo, Khue Duong: ESD protection circuit. Xilinx, Anthony C Wagner Murabito & Hao Murabito Esq, Edel M Young Xilinx, November 18, 1997: US05689133 (32 worldwide citation)

An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures a ...