1
Alfred J Reich, Kevin D Lucas, Michael E Kling, Warren D Grobman, Bernard J Roman: One dimensional lithographic proximity correction using DRC shape functions. Motorola, Daniel D HIll, May 4, 1999: US05900340 (196 worldwide citation)

Integrated circuit designs are continually shrinking in size. Lithographic processes are used to pattern these designs onto a semiconductor substrate. These processes typically require that the wavelength of exposure used during printing be significantly shorter than the smallest dimension of the el ...


2

3
Kevin D Lucas, Michael E Kling, Alfred J Reich, Chong Cheng Fu, James Morrow: Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same. Motorola, J Gustav Larson, December 15, 1998: US05849440 (40 worldwide citation)

A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lit ...


4
Alfred J Reich, Warren D Grobman, Bernard J Roman, Kevin D Lucas, Clyde H Browning, Michael E Kling: Two dimensional lithographic proximity correction using DRC shape functions. Motorola, Bruce E Hayden, July 6, 1999: US05920487 (36 worldwide citation)

Integrated circuit designs are continually shrinking in size. Lithographic processes are used to transfer these designs to a semiconductor substrate. These processes typically require that the exposure wavelength of light be shorter than the smallest dimension of the elements within the circuit desi ...


5
Yonchan Ban, Kevin D Lucas: Method and apparatus for determining mask layouts for a spacer-is-dielectric self-aligned double-patterning process. Synopsys, Park Vaughan Fleming & Dowler, Laxman Sahasrabuddhe, November 13, 2012: US08312394 (22 worldwide citation)

Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, ...


6
Kevin D Lucas, Jonathan L Cobb, William L Wilkinson: Non-resolving mask tiling method for flare reduction. Freescale Semiconductor, Robert L King, James L Clingan Jr, January 24, 2006: US06989229 (20 worldwide citation)

Photoresist on a wafer is exposed using tiles on a mask that improve flare performance. Features that are not to be exposed on the photoresist correspond to features on the mask. The various features are surrounded by other features that vary and thus affect flare differently. Selected features have ...


7

8
Kevin D Lucas, Robert E Boone, Mehul D Shroff, Kirk J Strozewski, Chi Min Yuan, Jason T Porter: Layout modification using multilayer-based constraints. Freescale Semiconductor, Michael J Balconi Lamica, October 16, 2007: US07284231 (6 worldwide citation)

A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features ...


9
Kevin D Lucas, William L Wilkinson, Cesar Garza: Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer. Motorola, Kim Marie Vo, Daniel D Hill, November 18, 2003: US06649452 (5 worldwide citation)

A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. After the location of design and processing features is determined, subresolution features are formed in areas devoid of design and processing fea ...


10
Olubunmi O Adetutu, Kevin D Lucas: Semiconductor device and method of forming the same. Freescale Semiconductor, Michael J Balconi Lamica, Joanna G Chiu, August 23, 2005: US06933227 (1 worldwide citation)

A process for forming a semiconductor structure includes forming a gate dielectric overlying a substrate, a conductive gate electrode overlying the gate dielectric, a barrier layer overlying and in physical contact with the conductive gate electrode, and an organic anti-reflective coating (ARC) laye ...