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Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi: Method of fabricating semiconductor device. Hitachi, Hitachi ULSI Systems, Mattingly Stanger & Malur P C, January 2, 2001: US06168996 (138 worldwide citation)

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a ...


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Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi: Insulated gate type semiconductor device and method for fabricating the same. Renesas Technology, Hitachi Tobu Semiconductor, Miles & Stockbridge P C, April 22, 2008: US07361557 (19 worldwide citation)

In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is con ...


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Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi: Insulated gate type semiconductor device and method for fabricating the same. Renesas Technology, Hitachi Tobu Semiconductor, Miles & Stockbridge P C, February 22, 2005: US06858896 (10 worldwide citation)

In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is con ...


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Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi: Method of fabricating semiconductor device. Hitachi, Hitachi ULSI Systems, Mattingly Stanger & Malur P C, October 23, 2001: US06307231 (9 worldwide citation)

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a ...


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Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi: Method of fabricating semiconductor device. Renesas Technology, Hitachi ULSI Systems, Mattingly Stanger & Malur P C, October 12, 2004: US06803281 (7 worldwide citation)

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a ...


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Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi: Method of fabricating semiconductor device. Hitachi, Hitachi ULSI Systems, Mattingly Stanger & Malur P C, June 25, 2002: US06410959 (6 worldwide citation)

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a ...


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Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi: Method of fabricating semiconductor device. Renesas Technology, Hitachi ULSI Systems, Mattingly Stanger & Malur P C, April 13, 2004: US06720220 (4 worldwide citation)

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a ...


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Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi: Method of fabricating semiconductor device. Hitachi, Hitachi ULSI Systems, Mattingly Stanger & Malur P C, January 28, 2003: US06512265 (4 worldwide citation)

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a ...


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Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi: Insulated gate type semiconductor device and method for fabricating the same. Renesas Technology, Hitachi Tobu Semiconductor, Miles & Stockbridge P C, February 6, 2007: US07172941 (3 worldwide citation)

In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is con ...