1
Katherina Babich
Deok kee Kim, Kenneth T Settlemyer Jr, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P Mahorowala, Harald Okorn Schmidt: Methods and structures for protecting one area while processing another area on a chip. International Business Machines Corporation, Whitman Curtis Christofferson & Cook PC, Joseph P Abate, March 3, 2009: US07497959 (4 worldwide citation)

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided whi ...


2
Daria R Dooling, Kenneth T Settlemyer Jr, Jacek G Smolinski, Stephen D Thomas, Ralph J Williams: Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Ryan K Simmons Esq, October 7, 2008: US07434185 (168 worldwide citation)

A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined mar ...


3
Jochen C Beintner, Dureseti Chidambarrao, Yujun Li, Kenneth T Settlemyer Jr: Pull-back method of forming fins in FinFets. International Business Machines Corporation, Eric W Petraske, March 28, 2006: US07018551 (54 worldwide citation)

A method of forming integrated circuits having FinFET transistors includes a method of forming sub-lithographic fins, in which a mask defining a block of silicon including a pair of fins in reduced in width or pulled back by the thickness of one fin on each side, after which a second mask is formed ...


4
Yujun Li, Kenneth T Settlemyer Jr, Jochen Beintner: Device fabrication by anisotropic wet etch. International Business Machines Corporation, George Sai Halasz, Robert M Trepp, August 12, 2008: US07410844 (38 worldwide citation)

A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crys ...


5
Michael P Chudzik, Johnathan Faltermeier, Rajarao Jammy, Stephan Kudelka, Irene McStay, Kenneth T Settlemyer Jr, Helmut Horst Tews: Process flow for capacitance enhancement in a DRAM trench. International Business Machines Corporation, Steven Capella Esq, Scully Scott Murphy & Presser, April 29, 2003: US06555430 (19 worldwide citation)

Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portio ...


6
Oh Jung Kwon, Kenneth T Settlemyer Jr, Ravikumar Ramachandran, Min Soo Kim: Method of fabricating a bottle trench and a bottle trench capacitor. International Business Machines Corporation, Infineon Technologies, Steven Capella, October 17, 2006: US07122439 (15 worldwide citation)

A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to ...


7
Kangguo Cheng, Ramachandra Divakaruni, Kenneth T Settlemyer Jr: Replacement gate with TERA cap. International Business Machines Corporation, Eric W Petraske, Yuanmin Cai, November 21, 2006: US07138308 (13 worldwide citation)

A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patte ...


8
Michael Patrick Chudzik, Jack Allan Mandelman, Carl John Radens, Rajarao Jammy, Kenneth T Settlemyer Jr, Padraic C Shafer, Joseph F Shepard Jr: Method and structure for salicide trench capacitor plate electrode. International Business Machines Corporation, Joseph P Abate, Daryl K Neff, December 16, 2003: US06664161 (12 worldwide citation)

The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form ...


9
Hiroyuki Akatsu, Oleg Gluschenkov, Porshia S Parkinson, Ravikumar Ramachandran, Helmut Horst Tews, Kenneth T Settlemyer Jr: Vertical hard mask. International Business Machines Corporation, Daryl Neff, April 20, 2004: US06723611 (6 worldwide citation)

In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower ...


10
Michael P Chudzik, Rajarao Jammy, Carl John Radens, Kenneth T Settlemyer Jr, Padraic Shafer, Joseph F Shepard Jr: Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric. International Business Machines Corporation, Daryl K Neff, August 30, 2005: US06936512 (5 worldwide citation)

Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a por ...



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