1
Kenneth J Mobley: Non-volatile memory cell and sensing method. Ramtron Corporation, Edward D Manzo, December 19, 1989: US04888733 (137 worldwide citation)

A ferroelectric memory cell has one capacitor isolated from bit lines by two transistors, one on each side. The cell is read by pulsing the capacitor in one direction, then the other, storing developed charge on other capacitors or the like, and comparing voltages.


2
Ronald H Sartore, Kenneth J Mobley, Donald G Carrigan, Oscar Frederick Jones: Enhanced DRAM with all reads from on-chip cache and all writers to memory array. Ramtron International Corporation, Richard A Bachand Esq, William J Kubida Esq, Peter J Meza Esq, December 16, 1997: US05699317 (124 worldwide citation)

An enhanced dynamic random access memory (DRAM) contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these register ...


3
Ronald H Sartore, Kenneth J Mobley, Donald G Carrigan, Oscar Frederick Jones: Enhanced DRAM with embedded registers. Enhanced Memory Systems, Peter J Meza, Michael R Casey, William J Kubida, March 23, 1999: US05887272 (59 worldwide citation)

An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data ...


4
Jim L Rogers, Steven W Tomashot, David W Bondurant, Oscar Frederick Jones Jr, Kenneth J Mobley: Cached synchronous DRAM architecture having a mode register programmable cache policy. International Business Machines, Francis J Thornton, Robert A Walsh, September 11, 2001: US06289413 (59 worldwide citation)

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode ...


5
Ronald H Sartore, Kenneth J Mobley, Donald G Carrigan, Oscar Frederick Jones Jr: Enhanced DRAM with single row SRAM cache for all device read operations. Ramtron International Corporation, William J Kubida Esq, Richard A Bachand Esq, Peter J Meza Esq, February 24, 1998: US05721862 (58 worldwide citation)

An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data ...


6
Kim C Hardee, Kenneth J Mobley: Low-to-high voltage translator with latch-up immunity. United Memories, Nippon Steel Semiconductor Corporation, Edward D Manzo, David K Lucente, June 14, 1994: US05321324 (41 worldwide citation)

A fast low-to-high voltage translator with immunity to latch-up. The circuit includes a voltage comparator and employs at least one transistor which is used to quickly pull up a node. If further uses another transistor which is capable of limiting the voltage at certain nodes in order to eliminate l ...


7
David W Bondurant, Michael Peters, Kenneth J Mobley: Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank. Enhanced Memory Systems, William J Kubida Esq, Peter J Meza Esq, Kent Lembke Esq, December 11, 2001: US06330636 (28 worldwide citation)

A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) device incorporating a static random access memory (“SRAM”) cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventiona ...


8
Michael Alwais, Kenneth J Mobley: Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control. Enhanced Memory Systems, William J Holland & Hart Kubida Esq, November 23, 1999: US05991851 (20 worldwide citation)

An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memo ...


9
Kenneth J Mobley: Current sensing differential amplifier. INMOS Corporation, Edward D Manzo, August 23, 1988: US04766333 (15 worldwide citation)

An amplifier for a semiconductor circuit provides two circuit paths between VCC and ground, each including the source-drain path of a corresponding primary transistor. Two inpedances are coupled to respective inputs. The primary transistors are kept in saturation so that the voltage differential bet ...


10
Kenneth J Mobley: Structure and method for hiding DRAM cycle time behind a burst access. Enhanced Memory Systems, William J Kubida Esq, Peter J Meza Esq, Hogan & Hartson, December 31, 2002: US06501698 (14 worldwide citation)

A method and system for hiding DRAM cycle time behind burst read and write accesses. A combined read and write data transfer area interacts with a set of sense amplifiers to accelerate read and write cycles. By independently isolating the read data transfer areas and the write data transfer areas, d ...