1
Michio Morioka, Kenichi Kurosawa, Tetsuaki Nakamikawa, Sakoh Ishikawa: Multiprocessor system having controller for controlling the number of processors for which cache coherency must be guaranteed. Hitachi, Antonelli Terry Stout & Kraus, October 7, 2003: US06631447 (109 worldwide citation)

To provide a large scale multiprocessor system capable of executing an area limited cache coherency control implementing a high speed operation while substantially reducing the amount of processor-to-processor communications there is provided a translation lookaside buffer which retains cache cohere ...


2
Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Tadaaki Bandoh, Masahiro Iwamura, Takashi Hotta, Yasuhiro Nakatsuka, Shigeya Tanaka, Takeshi Takemoto: Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory. Hitachi, Antonelli Terry Stout & Kraus, July 21, 1998: US05784630 (65 worldwide citation)

A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of ...


3
Tetsuaki Nakamikawa, Shin Kokura, Kenichi Kurosawa, Shinichiro Yamaguchi, Yoshihiro Miyazaki, Hiroshi Ohguro: Dual information processing system having a plurality of data transfer channels. Hitachi, Pennie & Edmonds, November 24, 1998: US05841963 (36 worldwide citation)

A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer ch ...


4
Katsuhiko Odajima, Kenichi Kurosawa: Suck back valve with sucking amount control mechanism. SMC Kabushiki Kaisha, Oblon Spivak McClelland Maier & Neustadt P C, November 23, 1999: US05988524 (35 worldwide citation)

A suck back valve is equipped with a second valve by which a flow amount of a pressurized fluid, which is sucked by a third diaphragm, is electrically controlled based on an output of activation and deactivation signals from a main controller. The suck back valve further includes an encoder which de ...


5
Shuuichi Miura, Kenichi Kurosawa, Tetsuaki Nakamikawa, Kenji Hirose: Prefetch buffer and information processing system using the same. September 6, 1994: US05345560 (35 worldwide citation)

A prefetch buffer adapted to be installed between a cache memory and a main memory in a computer system having a CPU. The prefetch buffer includes a buffer storage having at least one entry for storing prefetched data and an address tag, which is to be used for searching the data, as a pair; a data ...


6
Koji Matsuda, Soichi Takaya, Yoshihiro Miyazaki, Kenichi Kurosawa, Shinichiro Yamaguchi, Sako Ishikawa, Akira Yamagiwa, Masao Inoue, Kenji Kashiwagi: Uninterruptible clock supply apparatus for fault tolerant computer system. Hitachi, Kenyon & Kenyon, December 22, 1998: US05852728 (33 worldwide citation)

The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the ...


7
Hiroshi Ohguro, Koichi Ikeda, Takaaki Nishiyama, Hiroshi Iwamoto, Kenichi Kurosawa, Tetsuaki Nakamikawa, Michio Morioka: Fault recovering system provided in highly reliable computer system having duplicated processors. Hitachi, Antonelli Terry Stout & Kraus, May 5, 1998: US05748873 (30 worldwide citation)

A highly reliable computer system is intended to duplicate processors, compare the outputs of the processors with each other and enhance the validity of the output of processor system. If a mismatch between the outputs is detected, one of the processors performs a process of saving an internal state ...


8
Kenichi Kurosawa, Shigeya Tanaka, Yasuhiro Nakatsuka, Tadaaki Bandoh: Parallel processing apparatus and method capable of processing plural instructions in parallel or successively. Hitachi, Antonelli Terry Stout & Kraus, October 1, 1996: US05561775 (29 worldwide citation)

A parallel processing apparatus which includes a program counter for indicating instructions to be read out from a memory, an instruction register for storing a plurality of consecutive instructions read out from an address of the memory indicated by the program counter, a plurality of integer logic ...


9
Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Tadaaki Bandoh, Masahiro Iwamura, Takashi Hotta, Yasuhiro Nakatsuka, Shigeya Tanaka, Takeshi Takemoto: Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory. Hitachi, Antonelli Terry Stout & Kraus, October 19, 1999: US05968160 (29 worldwide citation)

A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of ...


10
Kentaro Yoshimura, Kohei Sakurai, Nobuyasu Kanekawa, Yuichiro Morita, Yoshiaki Takahashi, Kenichi Kurosawa, Toshimichi Minowa, Masatoshi Hoshino, Yasuhiro Nakatsuka, Kotaro Shimamura, Kunihiko Tsunedomi, Shoji Sasaki: Vehicle control system. Hitachi, Crowell & Moring, February 4, 2014: US08645022 (28 worldwide citation)

A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least ...