1
Kelvin S Vartti, Mitchell A Bauman: Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues. Unisys Corporation, Charles A Johnson, Mark T Starr, October 14, 1997: US05678026 (84 worldwide citation)

A storage lock apparatus for a multiprocessor data processing system. The storage lock apparatus includes control for granting locks to different selectable portions of storage in parallel. In addition, acknowledgment from a remote lock controller is not required for a processor to obtain a lock on ...


2
Kelvin S Vartti, Ross M Weber, Mitchell A Bauman: Programmable system and method for accessing a shared memory. Unisys Corporation, Beth L McMahon, Charles A Johnson, Richard J Gregson, August 21, 2007: US07260677 (25 worldwide citation)

A memory control system and method is disclosed. In one embodiment, a first memory is coupled to one or more additional memories. The first memory receives requests for data that are completed by retrieving the data from the first memory and/or the one or more additional memories. The manner in whic ...


3
Kelvin S Vartti: Method and apparatus for controlling memory storage locks based on cache line ownership. Unisys Corporation, Charles A Johnson, Mark T Starr, Crawford Maunu PLLC, September 23, 2003: US06625698 (20 worldwide citation)

A system and method for controlling storage locks based on cache line ownership. Ownership of target data segments is acquired at a memory targeted by a first requesting device. A storage lock is enabled that prohibits requesting devices, other than the first requesting device, from acting on the ta ...


4
Donald W Mackenthun, Kelvin S Vartti: Cache control system for performing multiple outstanding ownership requests. Unisys Corporation, Beth L McMahon, Michael B Atlass, Charles A Johnson, April 16, 2002: US06374332 (15 worldwide citation)

An improved directory-based, hierarchical memory system is disclosed that is capable of simultaneously processing multiple ownership requests initiated by a processor that is coupled to the memory. An ownership request is initiated on behalf of a processor to obtain an exclusive copy of memory data ...


5
Kelvin S Vartti, Ross M Weber: Programmable cache management system and method. Unisys Corporation, Charles A Johnson, Robert Marley, February 24, 2009: US07496715 (14 worldwide citation)

A memory control system and method is disclosed. The system includes cache tag logic and an optional cache coupled to a main memory. If available, the cache retains a subset of the data stored within the main memory. This subset is selected by programmable control indicators. These indicators furthe ...


6
Donald C Englin, Kelvin S Vartti: System and method for increasing cache hit detection performance. Unisys Corporation, Charles A Johnson, Mark T Starr, Hollingsworth & Funk, October 10, 2006: US07120836 (13 worldwide citation)

A system and method for increasing computing throughput through execution of parallel data error detection/correction and cache hit detection operations. In one path, hit detection occurs independent of and concurrent with error detection and correction operations, and reliance on hit detection in t ...


7
Kelvin S Vartti, Gregory B Wiedenman: Detection of skew fault in a multiple clock system. Unisys Corporation, Glenn W Bowen, Mark T Starr, Charles A Johnson, January 10, 1995: US05381416 (12 worldwide citation)

A skew fault detection system for detecting clock skew between two clock phases utilizes a plurality of skew fault detection circuits each of which employs two D-type flip-flops. The clock terminals of both of these flip-flops are connected to one of the clock phases, and one of the clock phases is ...


8
James A Williams, Robert H Andrighetti, Conrad S Shimada, Donald C Englin, Kelvin S Vartti: Data pre-fetch system and method for a cache memory. Unisys Corporation, Beth L McMahon, Charles A Johnson, Mark T Starr, January 31, 2006: US06993630 (11 worldwide citation)

A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines whether the ...


9
Kelvin S Vartti, Thomas T Kubista, Ferris T Price deceased: Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs. Unisys Corporation, Nawrocki Rooney & Sivertson P A, November 12, 1996: US05574753 (10 worldwide citation)

A glitch free clock switching circuit which produces a predictable and specifiable number of clock pulses to the system elements when switching between clock signals, even during full operation. In addition, the present invention has the capability of only switching between clocks at times that coin ...


10
Kelvin S Vartti, Ross M Weber, Mitchell A Bauman, Ronald G Arnold: Data acceleration mechanism for a multiprocessor shared memory system. Unisys Corporation, Beth L McMahon, Charles A Johnson, Mark T Starr, December 6, 2005: US06973548 (10 worldwide citation)

A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, other read-only ...



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