1
Masanori Henmi, Kazushi Kurata: DRAM controller for graphics processing operable to enable/disable burst transfer. Panasonic Corporation, McDermott Will & Emery, July 14, 2009: US07562184 (63 worldwide citation)

An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interva ...


2
Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazuya Furukawa, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. Matsushita Electric Industrial, June 10, 2008: US07386707 (16 worldwide citation)

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register g ...


3
Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazuya Furukawa, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. Panasonic Corporation, Panasonic Patent Center, Dhiren Odedra, Kerry Culpepper, April 19, 2011: US07930520 (15 worldwide citation)

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register g ...


4
Masayuki Masumoto, Kazushi Kurata, Hideyo Tsuruta: Decoding apparatus and encoding apparatus with specific bit sequence deletion and insertion. Panasonic Corporation, Wenderoth Lind & Ponack L, February 23, 2010: US07668381 (7 worldwide citation)

The decoding apparatus in the present invention includes a memory operable to hold encoded data representing one of a compressed sound and a compressed image, a memory read-out unit operable to sequentially read out the encoded data from said memory, a match determining circuit operable to determine ...


5
Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazuya Furukawa, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. Panasonic Corporation, Panasonic Patent Center, Dhiren Odedra, Kerry Culpepper, April 5, 2011: US07921281 (4 worldwide citation)

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register g ...


6
Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazuya Furukawa, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. Panasonic Corporation, Panasonic Patent Center, Dhiren Odedra, Kerry Culpepper, August 23, 2011: US08006076 (1 worldwide citation)

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register g ...


7
Kazushi Kurata: Task switching based on the execution control information held in register groups. Panasonic Corporation, McDermott Will & Emery, October 18, 2011: US08042116 (1 worldwide citation)

In a processor including a plurality of register groups, while a task is being executed using one of the register groups, a context of a task to be executed next is restored into another one of the register groups. If the execution of the task currently being executed is suspended before the restora ...


8
Kazuya Furukawa, Nobuo Higaki, Hideyo Tsuruta, Kazushi Kurata, Shigeki Fujii, Kousuke Yoshioka, Hiroyuki Morishita: Data transfer apparatus, data transfer method, and program. Panasonic Corporation, Greenblum & Bernstein, May 11, 2010: US07716391 (1 worldwide citation)

A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the c ...


9
Kazushi Kurata: Data processing device that controls an overriding of a subsequent instruction in accordance with a conditional execution status updated by a sequencer. Matsushita Electric Industrial, Hamre Schumann Mueller & Larson P C, March 7, 2006: US07010670 (1 worldwide citation)

The invention provides a data processing device with which disadvantages due to instruction allocation and decreased memory when adding a condition specifying field for executing conditional instructions can be prevented, and in which pipeline hazards due to the non-fulfillment of conditions can be ...


10
Kazushi Kurata, Kazuya Furukawa, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Shigeki Fujii, Toshio Sugimura: Processor and program execution method capable of efficient program execution. SOCIONEXT, McDermott Will & Emery, November 21, 2017: US09823946

A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslot ...