1
Susumu Emori, Hidemi Nakajima, Susumu Igarashi, Kazuo Kobayashi: IC module and smart card. Toppan Printing, Armstrong Westerman & Hattory, April 30, 2002: US06378774 (252 worldwide citation)

A smart card comprises an IC module and an antenna for non-contact transmission. The IC module has both a contact-type function and a non-contact-type function. In the contact-type function, power reception and signal transmission/reception is effected via an electrical contact. In the non-contact-t ...


2
Tai Kawano, Hidetoshi Yarita, Kazuo Kobayashi: Light emitting display. Yoshichu Mannequin, Kazou Kobayashi, Wenderoth Lind & Ponack L, June 11, 2002: US06404131 (157 worldwide citation)

A light emitting display includes a display body made of a light diffusing resin material which comprises a transparent resin doped with a light diffusing material, and an LED lamp having an LED chip encapsulated in a mold member made of a light transmissive material and embedded in the display body ...


3
Takeshi Nishino, Shuji Nakamura, Koichi Kiryu, Kazuo Kobayashi: Pointing device. Nagano Fujitsu Component, Staas & Halsey, December 14, 2004: US06831629 (154 worldwide citation)

A pointing device including a base section, an operating section shiftably supported on the base section, a magnet carried on one of the base section and the operating section, and a magneto-electro transducer carried on the other of the base section and the operating section at a location close to ...


4
Kazuo Kobayashi, Takeshi Nakayama, Yasushi Terada: Data integrity verifying circuit for electrically erasable and programmable read only memory (EEPROM). Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc Becker & Shur, March 7, 1989: US04811294 (145 worldwide citation)

An EEPROM provided with a write/erase checking circuit comprising, a data detector for determining whether one byte in an input data contains a "0" (representing that a memory cell is not in an erase state); an address latch circuit and a data latch circuit which latch the address and the input data ...


5
Norihiko Misawa, Kazuo Kobayashi, Katsumi Nakamura, Shigeyuki Yamano: DNA sequences useful for the synthesis of carotenoids. Kirin Beer Kabushiki Kaisha, Ladas & Parry, July 4, 1995: US05429939 (94 worldwide citation)

Disclosed are DNA sequences which are useful for the synthesis of carotenoids such as lycopene, .beta.-carotene, zeaxanthin or zeaxanthin-diglucoside, that is, DNA sequences encoding carotenoid biosynthesis enzymes. These DNA sequences are the sequences 1-6 shown in the specification.


6
Yoshikazu Miyawaki, Masanori Hayashikoshi, Takeshi Nakayama, Kazuo Kobayashi, Yasushi Terada: Semiconductor integrated circuit having multiple self-test functions and operating method therefor. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc Becker & Shur, November 13, 1990: US04970727 (84 worldwide citation)

In a semiconductor integrated circuit such as a semiconductor memory device capable of operating in a special mode in addition to a standard operation mode, a high voltage detection circuit 10 detects a high voltage applied to one of control signal input terminals CS and outputs a detection signal H ...


7
Yoshinori Adachi, Kazuo Kobayashi, Masaji Ebihara: Personal communication apparatus with call switching modem and packet switching modem. Mitsubishi Denki Kabushiki Kaisha, Wolf Greenfield & Sacks P C, July 7, 1998: US05777991 (77 worldwide citation)

A personal communication apparatus is disclosed, which comprises a radio transmitter 64 and a radio receiver 66 for participating in communication, a microphone 60, a loudspeaker 61, a processor 90 as a controller for controlling call switching communication and packet switching communication, a ROM ...


8
Takeshi Nakayama, Yasushi Terada, Masanori Hayashikoshi, Kazuo Kobayashi, Yoshikazu Miyawaki: Semiconductor memory device having error correcting function. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, August 3, 1993: US05233610 (71 worldwide citation)

A semiconductor memory device comprises a memory array, a test mode detecting circuit, an address counter, a correction circuit, and a data counter. When a test mode enable signal is applied externally to the test mode detecting circuit, the address counter sequentially addresses the memory array. T ...


9
Kazuo Kobayashi, Yasushi Terada, Takeshi Nakayama: Nonvolatile content-addressable memory and operating method therefor. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc Becker & Shur, May 5, 1992: US05111427 (60 worldwide citation)

Each of memory cells in a nonvolatile content-addressable memory (CAM) comprises a first memory transistor connected to a first storage node, a second memory transistor connected to a second storage node, and a memory capacitor connected between said first and second storage nodes. The first storage ...


10
Takeshi Nakayama, Kazuo Kobayashi, Yasushi Terada: Nonvolatile semiconductor memory device and a writing method therefor. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc Becker & Shur, February 20, 1990: US04903236 (58 worldwide citation)

In an erase mode, a high DC voltage Vpp is applied to all of the word lines and zero volt is applied to all of the bit lines, whereby the contents of all of the memory transistors are simultaneously erased. In a write mode, which constitutes an essential feature of the present invention, zero volt i ...