1
Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake: SRAM having load transistor formed above driver transistor. Hitachi, Antonelli Terry Stout & Kraus, November 10, 1998: US05834851 (158 worldwide citation)

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and ...


2
Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki: SRAM with dual word lines overlapping drive transistor gates. Antonelli Terry Stout & Kraus, August 24, 1993: US05239196 (57 worldwide citation)

A MOSFET Static Random Access Memory (SRAM) cell has a symmetrical construction, with a pair of word lines. The word lines are in second level polysilicon, so that they may overlap the driving transistor gates which are in first level polysilicon.


3
Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Hashimoto, Akihiro Shimizu, Koichiro Ishibashi, Katsuro Sasaki, Katsuhiro Shimohigashi, Eiji Takeda, Yoshio Sakai, Takashi Nishida, Osamu Minato, Toshiaki Masuhara, Shoji Hanamura, Shigeru Honjo, Nobuyuki Moriwaki: Semiconductor memory device having flip-flop circuits. Hitachi, Hitachi VLSI Engineering Corporation, Antonelli Terry Stout & Kraus, July 21, 1992: US05132771 (41 worldwide citation)

A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each fli ...


4
Katsuro Sasaki, Katsuhiro Shimohigashi, Koichiro Ishibashi, Shoji Hanamura: Sense amplifier for a memory device. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, June 30, 1992: US05126974 (37 worldwide citation)

A MOS transistor sense amplifier employs cross coupled positive feedback for the load circuit of a differential amplifier with an equalizing switch at the amplifier output, and preferably also at the input. This basis amplifier circuit may be repeated in stages. When stages are employed, it is desir ...


5
Hirotsugu Kojima, Katsuro Sasaki: High speed, reduced power memory system implemented according to access frequency. Hitachi America, Flehr Hohbach Test Albritton & Herbert, November 11, 1997: US05687382 (30 worldwide citation)

A memory system including a first memory area (MEM-A) implemented using memory units including low threshold voltage transistors powered by a low supply voltage source, and a second memory area (MEM-B) implemented using memory units including higher threshold voltage cells powered by a higher supply ...


6
Katsuro Sasaki, Nobuyuki Moriwaki, Shigeru Honjo, Hideaki Nakamura: High speed semiconductor memory having a direct-bypass signal path. Hitachi, Hitachi VISI Engineering, Antonelli Terry Stout & Kraus, September 8, 1992: US05146427 (29 worldwide citation)

In a semiconductor memory, a latch circuit is arranged between the outputs of a sense amplifier and the inputs of a data output buffer. First pass-gates are arranged between the outputs of the sense amplifier and the latch circuit, while second pass-gates are arranged between the latch circuit and t ...


7
Katsuro Sasaki, Katsuhiro Shimohigashi, Shoji Hanamura: Semiconductor memory having redundancy circuit for relieving defects. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, June 4, 1991: US05021944 (27 worldwide citation)

A method and apparatus for quickly masking defective memory elements with substitute memory elements includes first and second memory blocks. The first memory block includes a first memory array and a second spare memory array. The second memory block includes a second memory array and a first spare ...


8
Shuji Ikeda, Katsuro Sasaki, Kouichi Nagasawa, Satoshi Meguro: Semiconductor memory device. Hitachi, Antonelli Terry Stout & Kraus, April 2, 1991: US05005068 (26 worldwide citation)

A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring bein ...


9
Koichiro Ishibashi, Katsuro Sasaki, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Hashimoto, Akihiro Shimizu: Highly stable semiconductor memory with a small memory cell area. Hitachi, Hitachi VLSI Engineering, Antonelli Terry Stout & Kraus, July 28, 1992: US05134581 (20 worldwide citation)

In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)<3 where L.sub.DEFF and W.sub.DEFF denote an effective channel length and an effective channel width of two driver MOSFETs 3 and 4 respectively, and L ...


10
Shoji Hanamura, Masaaki Kubotera, Katsuro Sasaki, Takao Oono, Kiyotsugu Ueda: Static type semiconductor memory with multi-stage sense amplifier. Hitachi, Hitachi VLSI Engineering, Kenyon & Kenyon, January 2, 1990: US04891792 (17 worldwide citation)

Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circ ...



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