1
Victor Chan, Kathryn W Guarini, Meikei Ieong: Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers. International Business Machines Corporation, Wan Yee Cheung Esq, Scully Scott Murphy & Presser, November 23, 2004: US06821826 (141 worldwide citation)

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D ...


2
Syed M Alam, Ibrahim M Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N Kudva, David S Kung, Mark A Lavin, Arifur Rahman: Three dimensional integrated circuit. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Rafael Perez Piniero Esq, December 25, 2007: US07312487 (117 worldwide citation)

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to ...


3
Syed M Alam, Ibrahim M Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N Kudva, David S Kung, Mark A Lavin, Arifur Rahman: Three dimensional integrated circuit and method of design. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Brian P Verminski Esq, May 25, 2010: US07723207 (85 worldwide citation)

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to ...


4
Bruce B Doris, Kathryn W Guarini, Meikei Ieong, Shreesh Narasimha, Kern Rim, Jeffrey W Sleight, Min Yang: High-performance CMOS devices on hybrid crystal oriented substrates. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph P Abate Esq, February 12, 2008: US07329923 (77 worldwide citation)

An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming t ...


5
Kathryn W Guarini, Meikei Ieong, Leathen Shi, Min Yang: Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes. International Business Machines Corporation, Wan Yee Cheung Esq, Scully Scott Murphy & Presser, December 14, 2004: US06830962 (59 worldwide citation)

The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top sem ...


6
Steven J Holmes, Charles Black, David J Frank, Toshiharu Furukawa, Mark C Hakey, David V Horak, William Hsioh Lien Ma, Keith R Milkove, Kathryn W Guarini: Semiconductor with nanoscale features. International Business Machines Corporation, Mark F Chadurjian, Cantor Colburn, January 14, 2003: US06506660 (58 worldwide citation)

Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode patt ...


7
Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W Guarini: Integration of strained Ge into advanced CMOS technology. International Business Machines Corporation, George Sai Halasz, Robert M Trepp, July 17, 2007: US07244958 (57 worldwide citation)

A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buf ...


8
Kathryn W Guarini, Louis L Hsu, Leathen Shi, Dinkar V Singh, Li Kong Wang: Method of fabricating silicon devices on sapphire with wafer bonding at low temperature. International Business Machines Corporation, Scully Scott Murphy & Presser, Robert M Trepp Esq, June 28, 2005: US06911375 (26 worldwide citation)

Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling subst ...


9
Steven J Holmes, Charles Black, David J Frank, Toshiharu Furukawa, Mark C Hakey, David V Horak, William Hsioh Lien Ma, Keith R Milkove, Kathryn W Guarini: Method for increasing the capacitance of a semiconductor capacitors. International Business Machines Corporation, Mark F Chadurjian, Cantor Colburn, March 19, 2002: US06358813 (24 worldwide citation)

Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode patt ...


10
Omer H Dokumaci, Bruce B Doris, Kathryn W Guarini, Suryanarayan G Hegde, MeiKei Ieong, Erin Catherine Jones: Self-aligned planar double-gate process by self-aligned oxidation. International Busniess Machines Corporation, Scully Scott Murphy & Presser P C, Ido Tuchman Esq, April 17, 2007: US07205185 (14 worldwide citation)

A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the ox ...



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