1
Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J Mayur, Amir Al Bayati, Andrew Nguyen: Semiconductor substrate process using a low temperature deposited carbon-containing hard mask. Applied Materials, Law Office of Robert M Wallace, January 29, 2008: US07323401 (84 worldwide citation)

A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern, and depositing a carbon-containi ...


2
Hiroji Hanawa, Tsutomu Tanaka, Kenneth S Collins, Amir Al Bayati, Kartik Ramaswamy, Andrew Nguyen: Chemical vapor deposition plasma process using plural ion shower grids. Applied Materials, Law Office of Robert M Wallace, November 6, 2007: US07291360 (79 worldwide citation)

A chemical vapor deposition process is carried out in a reactor chamber having a set of plural parallel ion shower grids that divide the chamber into an upper ion generation region and a lower process region, each of the ion shower grids having plural orifices in mutual registration from grid to gri ...


3
Hiroji Hanawa, Tsutomu Tanaka, Kenneth S Collins, Amir Al Bayati, Kartik Ramaswamy, Andrew Nguyen: Chemical vapor deposition plasma process using an ion shower grid. Applied Materials, Law Office of Robert M Wallace, July 17, 2007: US07244474 (75 worldwide citation)

A chemical vapor deposition process is carried out in a reactor chamber with an ion shower grid that divides the chamber into an upper ion generation region and a lower process region, the ion shower grid having plural orifices oriented in a non-parallel direction relative to a surface plane of the ...


4
Kartik Ramaswamy, Kwok Manus Wong, Ashish Bhatnagar, Mehran Moalem, Tony S Kaushal, Shamouil Shamouilian: Porous ceramic liner for a plasma source. Applied Materials, Charles S Guenzer, Joseph Bach, April 9, 2002: US06367412 (72 worldwide citation)

A plasma tube comprising a vacuum sealing ceramic outer tube, a porous ceramic insert disposed on the inside wall of the outer tube, and a source of high frequency radiation, for example, an RF coil wrapped around the tube, to excite gas flowing through the bore of the insert into a plasma. The inve ...


5
Hiroji Hanawa, Tsutomu Tanaka, Kenneth S Collins, Amir Al Bayati, Kartik Ramaswamy, Andrew Nguyen: Chemical vapor deposition plasma reactor having plural ion shower grids. Applied Materials, Law of Office of Robert M Wallace, April 13, 2010: US07695590 (71 worldwide citation)

A plasma reactor for processing a semiconductor workpiece includes a reactor chamber and a set of plural parallel ion shower grids that divide the chamber into an upper ion generation region and a lower reactor region, each of the ion shower grids having plural orifices in mutual registration from g ...


6
Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J Mayur, Amir Al Bayati, Andrew Nguyen: Semiconductor junction formation process including low temperature plasma deposition of an optical absorption layer and high speed optical annealing. Applied Materials, Law Office of Robert M Wallace, September 19, 2006: US07109098 (67 worldwide citation)

A method of forming semiconductor junctions in a semiconductor material of a workpiece includes ion implanting dopant impurities in selected regions of the semiconductor material, introducing an optical absorber material precursor gas into a chamber containing the workpiece, generating an RF oscilla ...


7
Dan Maydan, Randir P S Thakur, Kenneth S Collins, Amir Al Bayati, Hiroji Hanawa, Kartik Ramaswamy, Biagio Gallo, Andrew Nguyen: Fabrication of silicon-on-insulator structure using plasma immersion ion implantation. Applied Materials, Law Office of Robert M Wallace, May 17, 2005: US06893907 (64 worldwide citation)

A method of fabricating a silicon-on-insulator structure having a silicon surface layer in a semiconductor workpiece, is carried out by maintaining the workpiece at an elevated temperature and producing an oxygen-containing plasma in the chamber while applying a bias to the workpiece and setting the ...


8
Hiroji Hanawa, Kartik Ramaswamy, Kenneth S Collins, Amir Al Bayati, Biagio Gallo, Andrew Nguyen: Low temperature CVD process with selected stress of the CVD layer on CMOS devices. Applied Materials, Law Office of Robert M Wallace, July 1, 2008: US07393765 (63 worldwide citation)

Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out low tempera ...


9
Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J Mayur, Amir Al Bayati, Andrew Nguyen: Low temperature plasma deposition process for carbon layer deposition. Applied Materials, Law Office of Robert M Wallace, December 25, 2007: US07312162 (61 worldwide citation)

A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupli ...


10
Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J Mayur, Amir Al Bayati, Andrew Nguyen: Copper barrier reflow process employing high speed optical annealing. Applied Materials, Law Office of Robert M Wallace, December 25, 2007: US07312148 (60 worldwide citation)

A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high asp ...