1
Karl L Wang, Jin Uk Luke Shin: Pipelined fast-access floating gate memory architecture and method of operation. Motorola, Keith E Witek, Kent J Cooper, May 4, 1999: US05901086 (77 worldwide citation)

A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1X and 2X architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) an ...


2
Ker Wen Teng, Karl L Wang, Bich Yen Nguyen, Wei Wu: Integrated circuit trench cell. Motorola, John A Fisher, December 26, 1989: US04890144 (76 worldwide citation)

A multiple element integrated circuit trench cell having at least one vertical field effect transistor (FET) in a wall of a trench in a semiconductor substrate. The cell further comprises a central load device within the trench which is electrically connected to the vertical FET. The central load de ...


3
Karl L Wang: Interlayer contact for use in a static RAM cell. Motorola, Anthony J Sarli Jr, Jeffrey Van Myers, James L Clingan Jr, April 8, 1986: US04581623 (30 worldwide citation)

A CMOS static RAM, which has P channel transistors formed in a second polysilicon layer, N channel transistors formed in the substrate, and gates of both the N channel and P channel transistors formed in a first polysilicon layers, requires that ohmic contact be made between semiconductor material o ...


4
Karl L Wang, Mark D Bader: Output amplifying stage with power saving feature. Motorola, James L Clingan Jr, November 20, 1990: US04972374 (29 worldwide citation)

A memory uses address transition detection to reduce power consumption of the output amplification stage. The output amplification stage, which drives an output driver, has a series of stages which are disabled except when there is an address transition. When there is an address transition all of th ...


5
Mark D Bader, Kenneth W Jones, Karl L Wang, Ray Chang: Memory having a write enable controlled word line. Motorola, Daniel D Hill, December 7, 1993: US05268863 (15 worldwide citation)

A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into ...


6
Karl L Wang, Mark D Bader, Peter H Voss: Bit line equalization in a memory. Motorola, John A Fisher, Jeffrey Van Myers, James L Clingan Jr, June 14, 1988: US04751680 (13 worldwide citation)

A memory has a memory cells located at intersections of bit line pairs and word lines. During a write mode of the memory, the bit lines are at a maximum voltage separation. For a read to occur following a write, the bit lines must first be equalized. Because of the extent of the voltage separation d ...


7
Karl L Wang, Taisheng Feng: Low di/dt output buffer with improved speed. Motorola, James C Clingan Jr, Paul J Polansky, September 18, 1990: US04958086 (12 worldwide citation)

An output buffer in an integrated circuit comprising voltage regulator, a predriver, and an output stage. The integrated circuit comprises a chip and a package and interconnections therebetween. The voltage regulator is coupled to a first power supply voltage terminal and a second power supply volta ...


8
Mark Bader, Karl L Wang: High speed write technique for a memory. Motorola, John A Fisher, Jeffrey Van Myers, James L Clingan Jr, August 16, 1988: US04764900 (12 worldwide citation)

In a random access memory a write driver develops a full rail write signal which is coupled to the selected bit line pair via transmission gates. The bit lines are thus driven to full rail. This results in a faster rise time on the bit line which is driven to a logic high. With the faster rise time, ...


9
Karl L Wang, Lal C Sood: Semiconductor memory with divided word lines and shared sense amplifiers. Motorola, Jonathan P Meyer, January 10, 1989: US04797858 (10 worldwide citation)

A semiconductor memory device having a divided word line architecture in which each block of the memory array is divided into half-blocks and the half-blocks of each block are located on different halves of the device separated by the row decoder. A data line bussing scheme cooperates with this uniq ...


10
Karl L Wang, Mark D Bader: Memory with improved write mode to read mode transition. Motorola, John A Fisher Jeffrey Van Myers James L Clingan Jr, August 25, 1987: US04689771 (10 worldwide citation)

A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition ...