1
Russell C Brockmann, Karl Brummel: Method for enhanced functional testing of a processor using dynamic trap handlers. Hewlett Packard Company, July 21, 1998: US05784550 (9 worldwide citation)

During generation of a test case, in response to a predictable interrupt condition a dynamic portion of a dynamic trap handler is created. The static portion of the dynamic trap handler is generic trap handler code that is not dynamically created and performs such routine tasks as loading the trap n ...


2
Kevin Safford, Rohit Bhatia, Karl Brummel: System and method for responding to TLB misses. Hewlett Packard Development Company, August 5, 2008: US07409524 (8 worldwide citation)

The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being perfor ...


3
Karl Brummel: Method and apparatus for embedding operand synthesizing sequences in randomly generated tests. Hewlett Packard Company, June 23, 1998: US05771241 (5 worldwide citation)

In a conventional random test generator, instructions are generated, pushed onto a queue, and then popped off of the queue in generation order. The methods and apparatus disclosed herein provide a means of associating a delay with each generated instruction. Instructions are therefore popped off of ...


4
Shawn Walker, Donald C Soltis Jr, Karl Brummel: Cache memory system and method capable of adaptively accommodating various memory line sizes. Hewlett Packard Development Company, June 2, 2009: US07543113 (3 worldwide citation)

A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. T ...


5
Kevin Safford, Rohit Bhatia, Karl Brummel: System and method for responding to TLB misses. Hewlett Packard Company, February 22, 2007: US20070043929-A1

The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being perfor ...