61
Jin Cai, Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni: Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same. International Business Machines Corporation, Harrington & Smith, May 21, 2013: US08445356 (9 worldwide citation)

Disclosed is a method of forming a structure and a resulting structure. The method includes providing a semiconductor substrate; forming a first opening to a first depth in the semiconductor substrate; amorphizing semiconductor sidewalls of an upper portion of the first opening leaving unamorphized ...


62
Kangguo Cheng, Bruce B Doris: CMOS circuit with low-k spacer and stress liner. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, July 17, 2012: US08222100 (9 worldwide citation)

The present disclosure provides a method of forming a plurality of semiconductor devices, wherein low-k dielectric spacers and a stress inducing liner are applied to the semiconductor devices depending upon the pitch that separates the semiconductor devices. In one embodiment, a first plurality of f ...


63
Kangguo Cheng, Carl J Radens: Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure. International Business Machines Corporation, Joseph Petrokaitis, Roberts Mlotkowski Safran & Cole P C, February 22, 2011: US07892932 (9 worldwide citation)

A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for ...


64
Kangguo Cheng, Joseph Ervin, Jeffrey B Johnson, Pranita Kulkarni, Kevin McStay, Paul C Parries, Chengwen Pei, Geng Wang, Yanli Zhang: Isolation in CMOSFET devices utilizing buried air bags. International Business Machines Corporation, Alexander Viderman, Joseph Petrokaitis, Matthew C Zehrer, March 12, 2013: US08395217 (9 worldwide citation)

A semiconductor device structure having an isolation region and method of manufacturing the same are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate. A plurality of gates is formed on the SOI substrate. The semiconductor device structure further includes ...


65
Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Pranita Kulkarni: Controlled fin-merging for fin type FET devices. International Business Machines Corporation, George Sai Halasz, Louis J Percello, February 19, 2013: US08377759 (9 worldwide citation)

A method for fabricating FET devices is disclosed. The method includes forming continuous fins of a semiconductor material and fabricating gate structures overlaying the continuous fins. After the fabrication of the gate structures, the method uses epitaxial deposition to merge the continuous fins t ...


66
Kangguo Cheng, Bruce B Doris, Ying Zhang: Asymmetric FinFET devices. International Business Machines Corporation, George Sai Halasz, Louis J Percello, September 11, 2012: US08263446 (9 worldwide citation)

Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the th ...


67
Kangguo Cheng, Woo Hyeong Lee, Huilong Zhu: Strained HOT (hybrid orientation technology) MOSFETs. International Business Machines Corporation, Schmeiser Olsen & Watts, Steven Capella, October 21, 2008: US07439110 (9 worldwide citation)

A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semicon ...


68
Ruilong Xie, Xiuyu Cai Jr, Kangguo Cheng, Ali Khakifirooz: Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices. GLOBALFOUNDRIES, Williams Morgan & Amerson P C, September 3, 2013: US08524592 (9 worldwide citation)

One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the metho ...


69
Kangguo Cheng, Louis Lu Chen Hsu, Jack Allan Mandelman: Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. International Business Machines Corporation, Wood Herron & Evans, March 1, 2011: US07898014 (8 worldwide citation)

Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of ...


70
Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih Chao Yang: Replacement metal gate processing with reduced interlevel dielectric layer etch rate. International Business Machines Corporation, Cantor Colburn, Vazken Alexanian, October 1, 2013: US08546209 (8 worldwide citation)

A method of forming a semiconductor device structure includes forming an interlevel dielectric (ILD) layer over a semiconductor substrate and a dummy transistor gate structure formed on the substrate; infusing a shallow gas cluster ion beam (GCIB) layer in a top portion of the ILD layer; and removin ...



Click the thumbnails below to visualize the patent trend.