Ali Khakifirooz, Thomas N Adam, Kangguo Cheng, Alexander Reznicek: High density bulk fin capacitor. International Business Machines Corporation, Joseph P Abate, Howard M Cohn, September 23, 2014: US08841185 (10 worldwide citation)

A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors.

Keith Kwong Hon Wong, Kangguo Cheng, Dechao Guo, Pranita Kulkarni: Integrated circuit with replacement metal gates and dual dielectrics. International Business Machines Corporation, Howard M Cohn, H Daniel Schnurmann, October 16, 2012: US08288296 (10 worldwide citation)

A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric ...

Veeraraghavan S Basker, Kangguo Cheng, Bruce B Doris, Johnathan E Faltermeier, Sivananda K Kanakasabapathy, Hemant Adhikari: Spacer as hard mask scheme for in-situ doping in CMOS finFETs. International Business Machines Corporation, Globalfoundries, Scully Scott Murphy & Presser P C, Yuanmain Cal, April 16, 2013: US08420464 (10 worldwide citation)

A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure ...

Roger A Booth Jr, Kangguo Cheng, Jack A Mandelman, William R Tonti: Electrically programmable π-shaped fuse structures and methods of fabrication thereof. International Business Machines Corporation, Heslin Rothenberg Farley & Mesiti PC, October 30, 2007: US07288804 (10 worldwide citation)

Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second term ...

Kangguo Cheng, Thomas N Adam, Ali Khakifirooz, Alexander Reznicek: FinFET and method of fabrication. International Business Machines Corporation, Joseph Petrokaitis, Howard H Coho, March 17, 2015: US08981493 (10 worldwide citation)

An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral ...

Kangguo Cheng, Bruce B Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek: Gate-all-around nanowire MOSFET and method of formation. International Business Machines Corporation, Harrington & Smith, Louis J Percello, December 2, 2014: US08900951 (10 worldwide citation)

A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; formi ...

Kangguo Cheng, Jack Allan Mandelman: Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby. International Business Machines Corporation, Wood Herron & Evans, December 7, 2010: US07847323 (10 worldwide citation)

Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selec ...

Kangguo Cheng, Dureseti Chidambarrao: Method of manufacturing a strained silicon on a SiGe on SOI substrate. International Business Machines Corporation, Lisa Jaklitsch, Greenblum & Bernstein P L, April 18, 2006: US07029964 (9 worldwide citation)

A semiconductor device with an undercut relaxed SiGe layer having voids beneath the SiGe layer. The voids may be filled with a dielectric such as SiO2. A strained Si layer may be epitaxially grown on the relaxed SiGe layer to combine the benefits of a defect-free strained Si surface and a silicon-on ...

Kangguo Cheng, Herbert L Ho, Geng Wang: Methods involving silicon-on-insulator trench memory with implanted plate. International Business Machines Corporation, Cantor Colburn, Rosa Suazo, June 23, 2009: US07550359 (9 worldwide citation)

A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI layer, implanting ions into the substr ...

Hiroyuki Akatsu, Kangguo Cheng, Kenneth Settlemyer: Method and structure for improved trench processing. International Business Machines Corporation, Daryl K Neff, H Daniel Schnurmann, November 22, 2005: US06967136 (9 worldwide citation)

A method is provided for making a trench capacitor by forming a trench in a substrate. The trench is then widened and a sacrificial collar is formed on sidewalls of the widened trench. The trench is then vertically deepened to extend below the sidewalls of the sacrificial collar. Subsequently, a cap ...

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