51
Kangguo Cheng, Ramachandra Divakaruni: Method for forming buried plate of trench capacitor. International Business Machines Corporation, Steve Capella, November 29, 2005: US06969648 (12 worldwide citation)

A method for forming a buried plate in a trench capacitor is disclosed. The trench is completely filled with a dopant source material such as ASG. The dopant source material is then recessed and the collar material is deposited to form the collar in the upper portion of the trench. After drive-in of ...


52
Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Alexander Reznicek: FinFET structures having silicon germanium and silicon fins. International Business Machines Corporation, Daniel P Morris, Otterstedt Ellenbogen & Kammer, March 31, 2015: US08993399 (12 worldwide citation)

A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon lay ...


53
Veeraraghavan S Basker, Kangguo Cheng, Bruce B Doris, Johnathan E Faltermeier, Sivananda K Kanakasabapathy, Hemant Adhikari: Spacer as hard mask scheme for in-situ doping in CMOS finFETs. International Business Machines Corporation, Globalfoundries, Scully Scott Murphy & Presser P C, Yuanmain Cal, April 16, 2013: US08420464 (12 worldwide citation)

A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure ...


54
Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek: Channel-last replacement metal-gate vertical field effect transistor. INTERNATIONAL BUSINESS MACHINES CORPORATION, Cantor Colburn, Louis Percello, December 20, 2016: US09525064 (12 worldwide citation)

A method of making a vertical transistor includes forming a doped source on a substrate; depositing a sacrificial gate material on the source; forming a trench in the sacrificial gate material to expose the doped source; growing an epitaxial layer within the trench to form a channel region extending ...


55
Kangguo Cheng, Ramachandra Divakaruni, Jack Allan Mandelman: Semiconductor structures with body contacts and fabrication methods thereof. International Business Machines Corporation, Wood Herron & Evans, November 3, 2009: US07611931 (11 worldwide citation)

A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semico ...


56
Kangguo Cheng, Michael P Chudzik, Ramachandra Divakaruni, Geng Wang, Robert C Wong, Haining S Yang: Integration scheme for multiple metal gate work function structures. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, June 8, 2010: US07732872 (11 worldwide citation)

A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, w ...


57
Kangguo Cheng, Louis C Hsu, William R Tonti, Chih Chao Yang: FinFET fuse with enhanced current crowding. International Business Machines Corporation, Gibb & Riley, Richard M Kotulak Esq, June 25, 2013: US08471296 (11 worldwide citation)

A method forms an eFuse structure that has a pair of adjacent semiconducting fins projecting from the planar surface of a substrate (in a direction perpendicular to the planar surface). The fins have planar sidewalls (perpendicular to the planar surface of the substrate) and planar tops (parallel to ...


58
Jin Cai, Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni: Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same. International Business Machines Corporation, Harrington & Smith, May 21, 2013: US08445356 (11 worldwide citation)

Disclosed is a method of forming a structure and a resulting structure. The method includes providing a semiconductor substrate; forming a first opening to a first depth in the semiconductor substrate; amorphizing semiconductor sidewalls of an upper portion of the first opening leaving unamorphized ...


59
Xiuyu Cai, Ruilong Xie, Ali Khakifirooz, Kangguo Cheng: Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same. GlobalFoundries, International Business Machines Corporation, Ingrassia Fisher & Lorenz P C, December 30, 2014: US08921191 (11 worldwide citation)

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and ...


60
Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Tenko Yamashita: Method and structure for improving finFET with epitaxy source/drain. INTERNATIONAL BUSINESS MACHINES CORPORATION, Scully Scott Murphy & Presser P C, Daniel P Morris Esq, March 22, 2016: US09293459 (11 worldwide citation)

Isolation structures are formed to laterally surround a gate material block such that each sidewall of the gate material block abuts a corresponding sidewall of the isolation structures. Sidewalls of the gate material bock define ends of gate structures to be subsequently formed. The isolation struc ...