31
Kangguo Cheng, Bruce B Doris, Ying Zhang: Method and structure for forming finFETs with multiple doping regions on a same chip. International Business Machines Corporation, Tutunjian & Bitetto P C, Louis J Percello, September 20, 2011: US08021949 (13 worldwide citation)

A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantati ...


32
MaryJane Brodsky, Kangguo Cheng, Herbert L Ho, Paul C Parries, Kevin R Winstel: Deep trench capacitor in a SOI substrate having a laterally protruding buried strap. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph R Abate, February 15, 2011: US07888723 (13 worldwide citation)

A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the ...


33
Ruilong Xie, Xiuyu Cai Jr, Kangguo Cheng, Ali Khakifirooz: Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation. GLOBALFOUNDRIES, Williams Morgan & Amerson P C, September 24, 2013: US08541274 (13 worldwide citation)

In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial ...


34
Kangguo Cheng, Louis C Hsu, Jack A Mandelman, Carl Radens, William Tonti: SOI field effect transistor with a back gate for modulating a floating body. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, August 10, 2010: US07772649 (13 worldwide citation)

A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulato ...


35
Herbert L Ho, Kangguo Cheng, Yoichi Otani, Kevin R Winstel: Deep trench capacitor through SOI substrate and methods of forming. International Business Machines Corporation, Todd M C Li, Hoffman Warnick, August 18, 2009: US07575970 (13 worldwide citation)

Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into ...


36
Roger A Booth Jr, Kangguo Cheng, Toshiharu Furukawa, Chengwen Pei: Integrated circuit with finFETs and MIM fin capacitor. International Business Machines Corporation, David Cain, Roberts Mlotkowski Safran & Cole P C, April 16, 2013: US08420476 (12 worldwide citation)

An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; ...


37
Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G Shahidi: Stressed Fin-FET devices with low contact resistance. International Business Machines Corporation, George Sai Halasz, Louis J Percello, March 19, 2013: US08399938 (12 worldwide citation)

An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET dev ...


38
Kangguo Cheng: High-k/metal gate MOSFET with reduced parasitic capacitance. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, October 12, 2010: US07812411 (12 worldwide citation)

The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET ...


39
Stephen W Bedell, Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Pranita Kulkarni, Katherine L Saenger: Strained devices, methods of manufacture and design structures. International Business Machines Corporation, Matthew Zehrer, Roberts Mlotkowski Safran & Cole P C, July 16, 2013: US08486776 (12 worldwide citation)

Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe lay ...


40
Kangguo Cheng, Ramachandra Divakaruni: Method for forming buried plate of trench capacitor. International Business Machines Corporation, Steve Capella, November 29, 2005: US06969648 (12 worldwide citation)

A method for forming a buried plate in a trench capacitor is disclosed. The trench is completely filled with a dopant source material such as ASG. The dopant source material is then recessed and the collar material is deposited to form the collar in the upper portion of the trench. After drive-in of ...



Click the thumbnails below to visualize the patent trend.