31
Narasimhulu Kanike, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens: Integration of fin-based devices and ETSOI devices. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, August 7, 2012: US08236634 (15 worldwide citation)

Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on s ...


32
Jack A Mandelman, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Geng Wang: Dual port gain cell with side and top gated read transistor. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Todd M C Li Esq, December 2, 2008: US07459743 (15 worldwide citation)

A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. ...


33
Roger A Booth Jr, Kangguo Cheng, Toshiharu Furukawa, Chengwen Pei: Integrated circuit with finFETs and MIM fin capacitor. International Business Machines Corporation, David Cain, Roberts Mlotkowski Safran & Cole P C, April 16, 2013: US08420476 (14 worldwide citation)

An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; ...


34
Kangguo Cheng, Bruce B Doris, Ying Zhang: Method and structure for forming finFETs with multiple doping regions on a same chip. International Business Machines Corporation, Tutunjian & Bitetto P C, Louis J Percello, September 20, 2011: US08021949 (14 worldwide citation)

A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantati ...


35
MaryJane Brodsky, Kangguo Cheng, Herbert L Ho, Paul C Parries, Kevin R Winstel: Deep trench capacitor in a SOI substrate having a laterally protruding buried strap. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph R Abate, February 15, 2011: US07888723 (14 worldwide citation)

A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the ...


36
Kangguo Cheng: High-k/metal gate MOSFET with reduced parasitic capacitance. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, October 12, 2010: US07812411 (14 worldwide citation)

The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET ...


37
Kangguo Cheng, Bruce B Doris: CMOS circuit with low-k spacer and stress liner. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, July 17, 2012: US08222100 (14 worldwide citation)

The present disclosure provides a method of forming a plurality of semiconductor devices, wherein low-k dielectric spacers and a stress inducing liner are applied to the semiconductor devices depending upon the pitch that separates the semiconductor devices. In one embodiment, a first plurality of f ...


38
Kangguo Cheng, Ramachandra Divakaruni, Kenneth T Settlemyer Jr: Replacement gate with TERA cap. International Business Machines Corporation, Eric W Petraske, Yuanmin Cai, November 21, 2006: US07138308 (14 worldwide citation)

A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patte ...


39
Ali Khakifirooz, Thomas N Adam, Kangguo Cheng, Alexander Reznicek: High density bulk fin capacitor. International Business Machines Corporation, Joseph P Abate, Howard M Cohn, September 23, 2014: US08841185 (14 worldwide citation)

A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors.


40
Kangguo Cheng, Balasubramanian S Haran, Shom Ponoth, Theodorus E Standaert, Tenko Yamashita: MOS capacitors with a finfet process. International Business Machines Corporation, Tutunjian & Bitetto P C, Vazken Alexanian, November 12, 2013: US08581320 (14 worldwide citation)

Capacitors include a first electrical terminal that has fins formed from doped semiconductor on a top layer of doped semiconductor on a semiconductor-on-insulator substrate; a second electrical terminal that has an undoped material having bottom surface shape that is complementary to the first elect ...