Narasimhulu Kanike, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens: Integration of fin-based devices and ETSOI devices. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, August 7, 2012: US08236634 (15 worldwide citation)

Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on s ...

Jack A Mandelman, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Geng Wang: Dual port gain cell with side and top gated read transistor. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Todd M C Li Esq, December 2, 2008: US07459743 (15 worldwide citation)

A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. ...

Kangguo Cheng, Bruce B Doris, Ying Zhang: Method and structure for forming finFETs with multiple doping regions on a same chip. International Business Machines Corporation, Tutunjian & Bitetto P C, Louis J Percello, September 20, 2011: US08021949 (14 worldwide citation)

A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantati ...

MaryJane Brodsky, Kangguo Cheng, Herbert L Ho, Paul C Parries, Kevin R Winstel: Deep trench capacitor in a SOI substrate having a laterally protruding buried strap. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph R Abate, February 15, 2011: US07888723 (14 worldwide citation)

A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the ...

Kangguo Cheng, Bruce B Doris: CMOS circuit with low-k spacer and stress liner. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, July 17, 2012: US08222100 (14 worldwide citation)

The present disclosure provides a method of forming a plurality of semiconductor devices, wherein low-k dielectric spacers and a stress inducing liner are applied to the semiconductor devices depending upon the pitch that separates the semiconductor devices. In one embodiment, a first plurality of f ...

Kangguo Cheng, Ramachandra Divakaruni, Kenneth T Settlemyer Jr: Replacement gate with TERA cap. International Business Machines Corporation, Eric W Petraske, Yuanmin Cai, November 21, 2006: US07138308 (14 worldwide citation)

A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patte ...

Ali Khakifirooz, Thomas N Adam, Kangguo Cheng, Alexander Reznicek: High density bulk fin capacitor. International Business Machines Corporation, Joseph P Abate, Howard M Cohn, September 23, 2014: US08841185 (14 worldwide citation)

A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors.

Ruilong Xie, Xiuyu Cai Jr, Kangguo Cheng, Ali Khakifirooz: Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation. GLOBALFOUNDRIES, Williams Morgan & Amerson P C, September 24, 2013: US08541274 (14 worldwide citation)

In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial ...

Kangguo Cheng, Bruce B Doris, Ghavam G Shahidi: Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, December 27, 2011: US08084309 (14 worldwide citation)

A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semicond ...

Kangguo Cheng, Bruce B Doris, Pranita Kulkarni, Ghavam Shahidi: Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, May 1, 2012: US08169024 (14 worldwide citation)

A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin silicon on insulator (ETSOI) layer, i.e., a silicon containing layer having a thickness of less than 10.0 nm. In one embodiment, the method may begin with providing a substra ...

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