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MaryJane Brodsky, Kangguo Cheng, Herbert L Ho, Paul C Parries, Kevin R Winstel: Deep trench capacitor in a SOI substrate having a laterally protruding buried strap. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph R Abate, February 15, 2011: US07888723 (14 worldwide citation)

A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the ...


32
Kangguo Cheng, Ramachandra Divakaruni, Kenneth T Settlemyer Jr: Replacement gate with TERA cap. International Business Machines Corporation, Eric W Petraske, Yuanmin Cai, November 21, 2006: US07138308 (14 worldwide citation)

A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patte ...


33
Ruilong Xie, Xiuyu Cai Jr, Kangguo Cheng, Ali Khakifirooz: Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation. GLOBALFOUNDRIES, Williams Morgan & Amerson P C, September 24, 2013: US08541274 (14 worldwide citation)

In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial ...


34
Jack A Mandelman, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Geng Wang: Dual port gain cell with side and top gated read transistor. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Todd M C Li Esq, December 2, 2008: US07459743 (14 worldwide citation)

A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. ...


35
Narasimhulu Kanike, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens: Integration of fin-based devices and ETSOI devices. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, August 7, 2012: US08236634 (14 worldwide citation)

Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on s ...


36
Kangguo Cheng, Bruce B Doris, Ghavam G Shahidi: Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, December 27, 2011: US08084309 (14 worldwide citation)

A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semicond ...


37
Kangguo Cheng, Hiroyuki Akatsu, Rama Divakaruni: Integration scheme for enhancing capacitance of trench capacitors. International Business Machines Corporation, Margaret A Pepper, October 19, 2004: US06806138 (14 worldwide citation)

The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional bottling of the trench, hemispher ...


38
Roger A Booth Jr, Kangguo Cheng, Toshiharu Furukawa, Chengwen Pei: Integrated circuit with finFETs and MIM fin capacitor. International Business Machines Corporation, David Cain, Roberts Mlotkowski Safran & Cole P C, April 16, 2013: US08420476 (13 worldwide citation)

An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; ...


39
Kangguo Cheng: Asymmetric multi-gated transistor and method for forming. International Business Machines Corporation, Joseph J Petrokaitis, Hoffman Warnick, March 25, 2014: US08679906 (13 worldwide citation)

In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmet ...


40
Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G Shahidi: Stressed Fin-FET devices with low contact resistance. International Business Machines Corporation, George Sai Halasz, Louis J Percello, March 19, 2013: US08399938 (13 worldwide citation)

An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET dev ...



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