21
Kangguo Cheng, Xi Li, Richard S Wise: Process for finFET spacer formation. International Business Machines Corporation, Cantor Colburn, Yuanmin Cai, January 13, 2009: US07476578 (14 worldwide citation)

A process for finFET spacer formation generally includes depositing, in order, a conformal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively rem ...


22
Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam Shahidi: Raised source/drain structure for enhanced strain coupling from stress liner. International Business Machines Corporation, Jose Gutman, Thomas Grzesik, Fleit Gibbons Gutman Bongini & Bianco PL, December 25, 2012: US08338260 (14 worldwide citation)

A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adja ...


23
Oh Jung Kwon, Kangguo Cheng, Deok kee Kim, Carl J Radens: Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby. International Business Machines Corporation, Graham S Jones II, H Daniel Schnurmann, April 26, 2005: US06884715 (14 worldwide citation)

A method of forming a device including a conductor and a contact over a semiconductor substrate starts by depositing first dielectric and first hard mask layers on the substrate. Form a conductor slot through the hard mask and down into or through the first dielectric layer. Form a recessed conducto ...


24
Jack A Mandelman, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Geng Wang: Dual port gain cell with side and top gated read transistor. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Todd M C Li Esq, December 2, 2008: US07459743 (14 worldwide citation)

A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. ...


25
Kangguo Cheng, Bruce B Doris, Ghavam G Shahidi: Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, December 27, 2011: US08084309 (14 worldwide citation)

A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semicond ...


26
Roger A Booth Jr, Kangguo Cheng, Jack A Mandelman: FinFET with top body contact. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph P Abate Esq, June 23, 2009: US07550773 (14 worldwide citation)

FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconducto ...


27
Kangguo Cheng, Hiroyuki Akatsu, Rama Divakaruni: Integration scheme for enhancing capacitance of trench capacitors. International Business Machines Corporation, Margaret A Pepper, October 19, 2004: US06806138 (14 worldwide citation)

The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional bottling of the trench, hemispher ...


28
MaryJane Brodsky, Kangguo Cheng, Herbert L Ho, Paul C Parries, Kevin R Winstel: Deep trench capacitor in a SOI substrate having a laterally protruding buried strap. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph R Abate, February 15, 2011: US07888723 (13 worldwide citation)

A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the ...


29
Kangguo Cheng, Ramachandra Divakaruni, Kenneth T Settlemyer Jr: Replacement gate with TERA cap. International Business Machines Corporation, Eric W Petraske, Yuanmin Cai, November 21, 2006: US07138308 (13 worldwide citation)

A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patte ...


30
Kangguo Cheng, Johnathan E Faltermeier, Toshiharu Furukawa, Xuefeng Hua: Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor. International Business Machines Corporation, Gibb I P Law Firm, May 31, 2011: US07951657 (13 worldwide citation)

Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconducto ...



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