21
Roger A Booth Jr, MaryJane Brodsky, Kangguo Cheng, Chengwen Pei: Shallow trench capacitor compatible with high-K / metal gate. International Business Machines Corporation, Joseph P Abate, Howard M Cohn, January 25, 2011: US07875919 (16 worldwide citation)

Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an ar ...


22
Roger A Booth Jr, MaryJane Brodsky, Kangguo Cheng, Chengwen Pei: Embedded trench capacitor having a high-k node dielectric and a metallic inner electrode. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Yuanmin Cai, March 2, 2010: US07671394 (16 worldwide citation)

A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad ...


23
Roger A Booth Jr, Kangguo Cheng, Chandrasekharan Kothandaraman: Fin anti-fuse with reduced programming voltage. International Business Machines Corporation, Gibb I P Law Firm, October 4, 2011: US08030736 (16 worldwide citation)

A method forms an anti-fuse structure comprises a plurality of parallel conductive fins positioned on a substrate, each of the fins has a first end and a second end. A second electrical conductor is electrically connected to the second end of the fins. An insulator covers the first end of the fins a ...


24
Oh Jung Kwon, Kangguo Cheng, Deok kee Kim, Carl J Radens: Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby. International Business Machines Corporation, Graham S Jones II, H Daniel Schnurmann, April 26, 2005: US06884715 (16 worldwide citation)

A method of forming a device including a conductor and a contact over a semiconductor substrate starts by depositing first dielectric and first hard mask layers on the substrate. Form a conductor slot through the hard mask and down into or through the first dielectric layer. Form a recessed conducto ...


25
Kangguo Cheng, Bruce B Doris, Toshiharu Furukawa: Method for double pattern density. International Business Machines Corporation, Gibb I P Law Firm, January 31, 2012: US08105901 (15 worldwide citation)

A method deposits an undoped silicon layer on a primary layer, deposits a cap layer on the undoped silicon layer, patterns a masking layer on the cap layer, and patterns the undoped silicon layer into silicon mandrels. The method incorporates impurities into sidewalls of the silicon mandrels in a pr ...


26
Kangguo Cheng, Johnathan E Faltermeier, Toshiharu Furukawa, Xuefeng Hua: Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor. International Business Machines Corporation, Gibb I P Law Firm, May 31, 2011: US07951657 (15 worldwide citation)

Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconducto ...


27
Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam Shahidi: Raised source/drain structure for enhanced strain coupling from stress liner. International Business Machines Corporation, Jose Gutman, Thomas Grzesik, Fleit Gibbons Gutman Bongini & Bianco PL, December 25, 2012: US08338260 (15 worldwide citation)

A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adja ...


28
Roger A Booth Jr, Kangguo Cheng, Jack A Mandelman: FinFET with top body contact. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph P Abate Esq, June 23, 2009: US07550773 (15 worldwide citation)

FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconducto ...


29
Kangguo Cheng, Bruce B Doris, Ying Zhang: Method and structure for forming finFETs with multiple doping regions on a same chip. International Business Machines Corporation, Tutunjian & Bitetto P C, Louis J Percello, September 20, 2011: US08021949 (14 worldwide citation)

A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantati ...


30
MaryJane Brodsky, Kangguo Cheng, Herbert L Ho, Paul C Parries, Kevin R Winstel: Deep trench capacitor in a SOI substrate having a laterally protruding buried strap. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph R Abate, February 15, 2011: US07888723 (14 worldwide citation)

A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the ...



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