1
Ka Hing Fung, H Bernhard Pogge: Three-dimensional chip stacking assembly. International Business Machines Corporation, H Daniel Schnurmann, March 12, 2002: US06355501 (381 worldwide citation)

An assembly consisting of three dimensional stacked SOI chips, and a method of forming such integrated circuit assembly, each of the SOI chips including a handler making mechanical contact to a first metallization pattern making electrical contact to a semiconductor device. The metalized pattern, in ...


2
Ka Hing Fung: Method of reducing the extrinsic body resistance in a silicon-on-insulator body contacted MOSFET. International Business Machines Corporation, H Daniel Schnurmann, November 4, 2003: US06642579 (38 worldwide citation)

As the silicon-on-insulator field effect transistor (SOI FET) CMOS technology continues migrating towards thinner SOI thicknesses to reduce the parasitic capacitance and improve the short channel effects, it is known that the body resistance of body contacted MOSFETs increases correspondingly. The p ...


3
Shui Ming Cheng, Ka Hing Fung, Yin Pin Wang, Kuan Lun Cheng, Huan Tsung Huang: Method for manufacturing a semiconductor device having an improved disposable spacer. Taiwain Semiconductor Manufacturing Company, Slater & Matsil L, November 1, 2005: US06960512 (33 worldwide citation)

The present invention provides methods for manufacturing semiconductor devices. In one embodiment, the method includes forming a gate oxide over a substrate and a gate electrode over the gate oxide. The method also includes implanting impurities into the substrate using the gate electrode as an impl ...


4
Ka Hing Fung, Percy V Gilbert: Semiconductor device structure including multiple fets having different spacer widths. International Business Machines Corporation, Joseph P Abate, October 19, 2004: US06806584 (29 worldwide citation)

A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a spacer having a second width, the first width being different than said se ...


5
Ka Hing Fung: Self-aligned V-channel MOSFET. Taiwan Semiconductor Manufacturing, Duane Morris, September 28, 2010: US07804130 (22 worldwide citation)

Forming a high-κ/metal gate field effect transistor using a gate last process in which the channel region has a curved profile thus increasing the effective channel length improves the short channel effect. During the high-κ/metal gate process, after the sacrificial materials between the sidewall sp ...


6
Kaun Lun Cheng, Shui Ming Cheng, Yu Yuan Yao, Ka Hing Fung, Sun Jay Chang: Method for selectively forming strained etch stop layers to improve FET charge carrier mobility. Taiwan Semiconductor Manufacturing, Tung & Associates, May 22, 2007: US07220630 (22 worldwide citation)

A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a st ...


7
Ka Hing Fung: SOI circuit with dual-gate transistors. International Business Machines Corporation, Eric W Petraske, January 1, 2002: US06335214 (22 worldwide citation)

A dual-gate SOI transistor that has the back gate self-aligned to the front gate is formed on an SOI substrate by forming a conventional gate stack having an etch resistant layer on the top; growing epitaxial silicon on the upper surface of the silicon device layer, which leaves apertures on both si ...


8
Shui Ming Cheng, Ka Hing Fung, Kuan Lun Cheng, Yi Ming Sheu: Semiconductor device having high drive current and method of manufacture therefor. Taiwan Semiconductor Manufacturing Company, Haynes and Boone, June 9, 2009: US07545001 (15 worldwide citation)

A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface. A first one of the NMOS and PMOS devices incl ...


9
Ka Hing Fung, Atul C Ajmera, Victor Ku, Dominic J Schepis: Method for forming notch gate having self-aligned raised source/drain structure. International Business Machines Corporation, H Daniel Schnurmann, January 14, 2003: US06506649 (12 worldwide citation)

An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD ...


10
Kuo Cheng Ching, Ka Hing Fung, Zhiqiang Wu, Carlos H Diaz: Structure and method for SRAM FinFET device. Taiwan Semicondcutor Manufacturing Company, Haynes and Boone, December 29, 2015: US09224736 (9 worldwide citation)

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer d ...