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Jyh Cherng J Tzeng: Three-dimensional memory cell with integral select transistor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 16, 1990: US04964080 (87 worldwide citation)

A three-dimensional floating gate memory cell including an integral select gate transistor is disclosed. Source and drain are formed in a silicon substrate wherein the drain is formed under a slot which has been etched into the body of the substrate. In this way, the channel defined between the sour ...


2
Jyh Cherng J Tzeng: Method of making a three-dimensional memory cell with integral select transistor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 17, 1991: US05049515 (58 worldwide citation)

A three-dimensional floating gate memory cell including an integral select gate transistor is disclosed. Source and drain are formed in a silicon substrate wherein the drain is formed under a slot which has been etched into the body of the substrate. In this way, the channel defined between the sour ...


3
Jyh Cherng J Tzeng: Process for reducing program disturbance in EEPROM arrays. June 1, 1993: US05215934 (30 worldwide citation)

A method by which the gate oxide in an EEPROM device is selectively thickened over the channel region nearest to the drain so as to penalize erase-type behavior during programming of a selected cell. First the lattice structure in a portion of the channel near said drain region is intentionally dama ...


4
Jyh Cherng J Tzeng: Three-dimensional contactless non-volatile memory cell. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 5, 1992: US05111270 (19 worldwide citation)

A three-dimensional contactless non-volatile memory cell is described. The memory cell comprises a substrate, source/drain regions that function as buried bit-lines and define a channel therebetween, a floating gate disposed above and insulated from the channel, and a control gate disposed above and ...


5
Jyh Cherng J Tzeng: Architecture for erasing very small areas of flash EPROMs. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 30, 1993: US05199001 (19 worldwide citation)

An electrically programmable memory array including a plurality of memory cells for storing data aligned in rows and columns, a plurality of word lines each connected to the gate terminals of the memory cells in a particular row, a plurality of bit lines each connected to the drain terminals of the ...


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