Yasushi Fukunaga, Tadaaki Bandoh, Hidekazu Matsumoto, Ryosei Hiraoka, Jushi Ide, Takeshi Kato, Tetsuya Kawakami: Shared virtual address translation unit for a multiprocessor system. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, November 6, 1984: US04481573 (110 worldwide citation)

A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to ex ...

Yasushi Fukunaga, Tadaaki Bandoh, Ryosei Hiraoka, Hidekazu Matsumoto, Jushi Ide, Tetsuya Kawakami: Bus selection control in a data transmission apparatus for a multiprocessor system. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, June 11, 1985: US04523272 (63 worldwide citation)

In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferr ...

Yasushi Fukunaga, Tadaaki Bandoh, Kotaro Hirasawa, Hidekazu Matsumoto, Jushi Ide, Takeshi Katoh, Hiroaki Nakanishi, Tetsuya Kawakami, Ryosei Hiraoka: Central processing unit for executing instructions of variable length having end information for operand specifiers. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, July 16, 1985: US04530050 (42 worldwide citation)

A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or ...

Yoshihiro Miyazaki, Jushi Ide, Takeshi Kato, Hiroaki Nakanishi, Tadaaki Bandoh: Multicomputer system having dual common memories. Hitachi, Antonelli Terry & Wands, November 8, 1988: US04783731 (32 worldwide citation)

A multicomputer system having dual common memories in which specified address areas are set within the common memories. The specified address areas are accessible irrespective of whether a CPU is in an online mode or a debug mode, while any area other than the specified address areas is accessible o ...

Sadao Mizokawa, Yoshiji Ito, Yasuo Hosoda, Hiroshi Kaita, Tadaaki Okada, Hiroaki Ohnishi, Seiichi Yasumoto, Hitoshi Fushimi, Jushi Ide, Hiroshi Kuwahara: Rotary type optical switch. Hitachi, Antonelli Terry & Wands, August 30, 1983: US04401365 (28 worldwide citation)

Disclosed is an optical switch of the rotary-type in which a pair of opposing optical transmission path mounting members are disposed on the same axis.

Takuji Hamada, Masahiro Takahashi, Kotaro Hirasawa, Jushi Ide, Hitoshi Fushimi, Seiichi Yasumoto: Loop transmission system having plural stations connected in a variable order. Hitachi, Antonelli Terry & Wands, August 23, 1988: US04766590 (26 worldwide citation)

A loop transmission system having a plurality of data processor connected through respective transmission station with a common loop transmission line is disclosed. This system has a concentrator connected with a plurality of transmission stations through respective loop transmission lines. The conc ...

Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Takayuki Morioka, Soichi Takaya, Yukio Kawamoto, Jushi Ide, Yoshihiro Miyazaki: Suspended instruction restart processing system based on a checkpoint microprogram address. Hitachi, Antonelli Terry Stout & Kraus, March 26, 1991: US05003458 (23 worldwide citation)

Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is ...

Masakazu Okada, Jushi Ide, Seiichi Yasumoto, Hitoshi Fushimi: Loop type data highway system. Hitachi, Craig & Antonelli, January 23, 1979: US04136384 (22 worldwide citation)

A loop type data highway system in which a plurality of data transmission control stations (abbreviated hereinafter as stations) are connected to a single loop transmission line for data transmission and reception between any desired ones. A transmit station transmitting data makes a compare check t ...

Yasuji Kamata, Hiroshi Kuwahara, Jushi Ide, Kenkichi Yamashita, Koji Takahashi: Convergence distortion correction method and apparatus for color cathode-ray tube. Hitachi, Antonelli Terry & Wands, August 30, 1983: US04401922 (21 worldwide citation)

In a convergence distortion correction method and apparatus for raster-scanned color CRT having a dynamic convergence magnet assembly, the CRT display screen is divided into a plurality of zones. A digital memory is provided with a data storage field and a flag bit field at each address. Addresses o ...

Takayuki Morioka, Jushi Ide: Printed circuit board capable of being inserted and withdrawn on on-line status. Hitachi, Craig and Antonelli, April 29, 1980: US04200865 (20 worldwide citation)

A printed circuit board loaded with an electronic circuit and constructed to be capable of being inserted in and withdrawn from a bus line on on-line status, in which the input to or the output from the printed circuit board is locked out in response to the presence of two conditions, one is the pre ...