1
Jung Herng Chang, Curt Berg, Jorge Cruz Rios: Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, March 14, 1995: US05398325 (78 worldwide citation)

Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a small internal cache memory structure. A subs ...


2
Pradeep S Sindhu, Bjorn Liencres, Jorge Cruz Rios, Douglas B Lee, Jung Herng Chang, Jean Marc Frailong: Apparatus and method for a synchronous, high speed, packet-switched bus. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, March 16, 1993: US05195089 (54 worldwide citation)

A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher cl ...


3
Hu H Chao, Jung Herng Chang: Pipelined error checking and correction for cache memories. International Business Machines Corporation, Whitham & Marhoefer, October 15, 1991: US05058116 (32 worldwide citation)

A single error correction, double error detection function for cache memories does not affect the normal cache access time the addition of the ECC function. Check bits are provided for multiple bytes of data, thereby lowering the overhead of the error detecting and correcting technique. When a singl ...


4
Jung Herng Chang, Curt Berg, Jorge Cruz Rios: Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, December 27, 1994: US05377345 (27 worldwide citation)

Apparatus and methods for a cache controller preserving cache consistency and providing multiple outstanding operations in a cache memory structure supporting a high performance central processor unit (CPU). An external cache array is coupled to both the CPU and a cache controller (CC), and is subbl ...


5
Jiande Jiang, Kenny Tseng, Walter C Lin, Jung Herng Chang: System and method for automatically controlling the phase of a clock signal for sampling an HDTV signal. Entropic Communications, Bruce Greenhaus, Richard Bachand, Duane Morris, November 19, 2013: US08587722 (1 worldwide citation)

The present invention provides a system and method for automatically controlling the phase of the clock signal for sampling an HDTV signal, which implements a new and improved method for phase detection. The system and method utilize the standard format of an HDTV signal to consistently ensure accur ...