1
Stefan Letz, Kai Weber, Juergen Vielfort: Verifying a processor design using a processor simulation model. International Business Machines Corporation, The Steadman Law Firm PLLC, Cynthia seal, August 21, 2012: US08249848 (3 worldwide citation)

An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each executi ...


2
Stefan Letz, Kai Weber, Juergen Vielfort: Verifying a processor design using a processor simulation model. International Business Machines Corporation, The Steadman Law Firm PLLC, Cynthia G Seal, Katherine S Brown, December 3, 2013: US08600724 (2 worldwide citation)

An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each executi ...


3
Stefan Letz, Juergen Vielfort, Kai Weber: Test case generation with backward propagation of predefined results and operand dependencies. International Business Machines Corporation, Randall Bluestone Esq, January 4, 2011: US07865793 (1 worldwide citation)

A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structure in a forwards manner, and calcu ...


4
Stefan Letz, Michelangelo Masini, Juergen Vielfort, Kai Weber: Verifying a register-transfer level design of an execution unit. International Business Machines Corporation, Francis Lammes, Stephen J Walder Jr, Libby Z Toub, March 19, 2013: US08402403

A mechanism is provided for verifying a register-transfer level design of an execution unit. A set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction rec ...


5
Stefan Letz, Michelangelo Masini, Juergen Vielfort, Kai Weber: Verifying a Register-Transfer Level Design of an Execution Unit. International Business Machines Corporation, June 23, 2011: US20110154110-A1

A mechanism is provided for verifying a register-transfer level design of an execution unit a set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction reco ...


6
Stefan Letz, Kai Weber, Juergen Vielfort: Method, System, computer program product and data processing program for verifying a processor Design. International Business Machines Corporation, Ibm Corporation, March 5, 2009: US20090063829-A1

An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model comprises at least one execution unit for executing at least one instruction of a test file. The method comprises tracking each execu ...


7
Stefan Letz, Kai Weber, Juergen Vielfort: Verifying a processor design using a processor simulation model. International Business Machines Corporation, November 8, 2012: US20120284007-A1

An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each executi ...