1
Thomas R Ermolovich, Robert E Stewart, Judson S Leonard, David N Cutler: Communications device for data processing system. Digital Equipment Corporation, Cesari and McKenna, March 9, 1982: US04319323 (120 worldwide citation)

A communications device transfers process data between a data processing system and an external device at high speed. The communications device receives command signals from a user process program in the data processing system and from the external device. The communications device generates physica ...


2
Neil C Wilhelm, Judson S Leonard: Apparatus and method for a pipelined central processing unit in a data processing system. Digital Equipment Corporation, William W Holloway, John G Mesaros, Ronald E Myrick, February 5, 1991: US04991078 (54 worldwide citation)

A data processing system is described in which the available technology is used to provide high performance. The high performance is achieved by having a four-level pipeline for the central processing system, a simplified instruction set and an interface with the coprocessor unit that has a simple a ...


3
Judson S Leonard, David Gingold, Lawrence C Stewart: System and method for remote direct memory access without page locking by the operating system. SiCortex, Chapin IP Law, Barry W Chapin Esq, May 12, 2009: US07533197 (37 worldwide citation)

A multi-node computer system with a plurality of interconnected processing nodes, including a method of using DMA engines without page locking by the operating system. The method includes a sending node with a first virtual address space and a receiving node with a second virtual address space. Perf ...


4
Silvio Turrini, Judson S Leonard, Norman P Jouppi: Floating point arithmetic system and method. Digital Equipment Corporation, Flehr Hohbach Test Albritton & Herbert, March 12, 1991: US04999803 (25 worldwide citation)

System and method for reducing the processing time or latency of floating point arithmetic operations by eliminating the need to complement a negative result produced by a subtraction operation. Each of two numbers is subtracted from the other in simultaneous parallel subtraction operations to produ ...


5
Neil C Wilhelm, Judson S Leonard: Apparatus and method for synchronization of a coprocessor unit in a pipelined central processing unit. Digital Equipment Corporation, William W Holloway, Michael A Glenn, July 24, 1990: US04943915 (22 worldwide citation)

In a data processing system with a central processing unit having a pipelined mode of operation, apparatus and method are disclosed for synchronizing the operation of a coprocessor unit with the remainder of the central processing unit, the remainder of the central processing unit being implemented ...


6
Judson S Leonard, Matthew H Reilly, Nitin Godiwala: System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels. SiCortex, Chapin IP Law, Barry W Chapin Esq, August 10, 2010: US07773618 (11 worldwide citation)

Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Ea ...


7
Stephen W Harston, Judson S Leonard: Integrated interpolator and method of operation. Analog Devices, Wolf Greenfield & Sacks, May 12, 1992: US05113362 (8 worldwide citation)

An interpolator circuit is formed from a chain of multiplexer/adder circuits. Each multiplexer/adder circuit selects one of the two multi-bit binary values which are to be interpolated in accordance with one bit of a multi-bit ratio value. The selected value is shifted and added to the output of a p ...


8
Robert A Eustace, Judson S Leonard: Chunky binary multiplier and method of operation. Digital Equipment Corporation, Flehr Hohbach Test Albritton & Herbert, July 5, 1994: US05327368 (5 worldwide citation)

A fast binary reduction tree of the type used in high speed digital computer multiplication circuits is disclosed having chunky adders formed by sub-dividing carry propagate adders into chunks of equal bit length such that chunk addition can be initiated in parallel. In the tree, chunky adders with ...


9
Judson S Leonard, Matthew H Reilly, Lawrence C Stewart, Washington Taylor: Computer system and method using a kautz-like digraph to interconnect computer nodes and having control back channel between nodes. SiCortex, Chapin IP Law, Barry W Chapin Esq, July 6, 2010: US07751344 (4 worldwide citation)

Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equal ...


10
Matthew H Reilly, Nitin Godiwala, Judson S Leonard: System and method for communicating on a richly connected multi-processor computer system using a pool of buffers for dynamic association with a virtual channel. SiCortex, Chapin IP Law, Barry W Chapin Esq, August 10, 2010: US07773616 (2 worldwide citation)

Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined int ...