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Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, R Michael Ananian, Dorsey & Whitney, April 6, 2004: US06717576 (151 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphic ...


2
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck: Graphics processor with deferred shading. Apple Computer, R Michael Ananian, Dorsey & Whitney, July 22, 2003: US06597363 (133 worldwide citation)

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage ...


3
Jerome F Duluk Jr, Jack Benkual, Shun Wai Go, Sushma S Trivedi, Richard E Hessel, Joseph P Bratt: Graphics processor with pipeline state storage and retrieval. Apple Computer, Dorsey & Whitney, February 25, 2003: US06525737 (112 worldwide citation)

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon ...


4
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck: Deferred shading graphics pipeline processor. Apple Computer, Flehr Hohbach Test Albritton & Herbert, May 8, 2001: US06229553 (86 worldwide citation)

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising a ...


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Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, Dorsey & Whitney, January 23, 2007: US07167181 (68 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphic ...


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Joseph P Bratt, John Brennen, Peter Y Hsu, Joseph T Scanlon, Man Kit Tang, Steven J Ciavaglia: Conflict resolution in interleaved memory systems with multiple parallel accesses. Silicon Graphics, Sterne Kessler Goldstein & Fox P L L C, April 14, 1998: US05740402 (63 worldwide citation)

A conflict resolution system for interleaved memories in processors capable of issuing multiple independent memory operations per cycle. The conflict resolution system includes an address bellow for temporarily storing memory requests, and cross-connect switches to variously route multiple parallel ...


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Jerome F Duluk, Stephen L Dodgen, Joseph P Bratt, Matthew Papakipos, Nathan Tuck, Richard E Hessel: Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor. Apple Computer, R Michael Ananian, Dorsey & Whitney, August 3, 2004: US06771264 (62 worldwide citation)

A system and method for performing tangent space lighting in a deferred shading graphics processor (DSGP) encompasses blocks of the DSGP that preprocess data and a Phong shader that executes only after all fragments have been preprocessed. A preprocessor block receives texture maps specified in a va ...


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Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck: Deferred shading graphics pipeline processor. Apple Computer, Flehr Hohbach Test Albritton & Herbert, July 31, 2001: US06268875 (60 worldwide citation)

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising ...


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Joseph P Bratt, John Brennan, Peter Y Hsu, William A Huffman, Joseph T Scanlon, Steve Ciavagia: System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes. Silicon Graphics, Sterne Kessler Goldstein & Fox P L L C, November 5, 1996: US05572704 (47 worldwide citation)

A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache t ...


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Jerome F Duluk Jr, Jack Benkual, Shun Wai Go, Sushma S Trivedi, Richard E Hessel, Joseph P Bratt: Graphics processor with pipeline state storage and retrieval. Apple Computer, R Michael Ananian, Dorsey & Whitney, February 17, 2004: US06693639 (46 worldwide citation)

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon ...