1
Thomas W Bachelder, Dennis R Barringer, Dennis R Conti, James M Crafts, David L Gardell, Paul M Gaschke, Mark R Laforce, Charles H Perry, Roger R Schmidt, Joseph J Van Horn, Wade H White: Segmented architecture for wafer test and burn-in. International Business Machines Corporation, William N Hogg, Robert A Walsh, August 14, 2001: US06275051 (60 worldwide citation)

An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distribut ...


2
Peter E Freiermuth, Kathleen S Ginn, Jeffrey A Haley, Susan J Lamaire, David A Lewis, Gavin T Mills, Timothy A Redmond, Yuk L Tsang, Joseph J Van Horn, Alfred Viehbeck, George F Walker, Jer Ming Yang, Clarence S Long: Method and apparatus for stressing, burning in and reducing leakage current of electronic devices using microwave radiation. International Business Machines Corporation, Daniel P Morris, May 21, 1996: US05519193 (14 worldwide citation)

The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging s ...


3
John Harold Magerlein, Samuel Roy McKnight, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Joseph J Van Horn, Richard Paul Volant, George Frederick Walker: Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same. International Business Machines Corporation, Ohlandt Greeley Ruggiero & Perle L, June 8, 2004: US06747472 (1 worldwide citation)

A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having t ...


4
Thomas W Bachelder, Dennis R Barringer, Dennis R Conti, James M Crafts, David L Gardell, Paul M Gaschke, Mark R Laforce, Charles H Perry, Roger R Schmidt, Joseph J Van Horn, Wade H White: Segmented architecture for wafer test & burn-in. International Business Machines Corporation, Driggs Lucas Brubaker & Hogg Co Lpa, December 13, 2001: US20010050567-A1

An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distribut ...


5
John Harold Magerlein, Samuel Roy McKnight, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Joseph J Van Horn, Richard Paul Volant, George Frederick Walker: Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same. International Business Machines Corporation, Paul D Greeley Esq, Ohlandt Greeley Ruggiero & Perle, July 24, 2003: US20030136813-A1

A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having t ...