1
Joseph C Circello, William A Hohl: Data processing system for performing a debug function and method therefor. Motorola, April 7, 1998: US05737516 (134 worldwide citation)

A data processor (3) executes a debug operation by minimally intruding on the real time operation of the data processor and without halting the data processor. The data processor implements a control register (40) which stores trigger response value for determining a function executed by the data pr ...


2
Alfred L Crouch, Matthew D Pressly, Joseph C Circello, Richard Duerden: Serial scan chain architecture for a data processing system and method of operation. Motorola, Keith E Witek, January 7, 1997: US05592493 (130 worldwide citation)

A scan chain architecture which has a controller (10), and a multiplexer (24) is used to route test data through functional units (12, 14, 16, 18, 20, and 22). The controller (10) receives as input a serial data stream from an STDI terminal and demultiplexes this data stream to one of the functional ...


3
Joseph C Circello, Richard H Duerden, Roger W Luce, Ralph H Olson: Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO. Edgcore Technology, Cahill Sutton & Thomas, March 31, 1992: US05101341 (111 worldwide citation)

A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanw ...


4
Joseph C Circello, Klaus R Riedel: Data processing system for performing a trace function and method therefor. Motorola, October 12, 1999: US05964893 (102 worldwide citation)

A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the dat ...


5
Gregory C Edgington, Joseph C Circello, Daniel M McCarthy, Richard Duerden: Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes. Motorola, Keith E Witek, June 25, 1996: US05530804 (95 worldwide citation)

A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of op ...


6
William A Hohl, Joseph C Circello: Data processing system for controlling execution of a debug function and method thereof. Motorola, Elizabeth A Apperley, J Gustav Larson, Michael P Noonan, February 15, 2000: US06026501 (65 worldwide citation)

A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) ...


7
Daniel M McCarthy, Joseph C Circello, Gabriel R Munguia, Nicholas J Richardson: Coherent cache structures and methods. Edgcore Technology, Cahill Sutton & Thomas, May 22, 1990: US04928225 (63 worldwide citation)

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly ...


8
Daniel M McCarthy, Joseph C Circello, Gabriel R Munguia, Nicholas J Richardson: Coherent cache structures and methods. Edge Computer Corporation, Cahill Sutton & Thomas, July 2, 1991: US05029070 (60 worldwide citation)

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly ...


9
Russell W Guenthner, Gregory C Edgington, Leonard G Trubisky, Joseph C Circello: Collector. Honeywell Information Systems, A A Sapelli, J S Solakian, A Medved, June 10, 1986: US04594660 (50 worldwide citation)

A collector for the results of a pipelined central processing unit of a digital data processing system. The processor has a plurality of execution units, with each execution unit executing a different set of instructions of the instruction repertoire of the processor. The execution units execute ins ...


10
William A Hohl, Joseph C Circello: Data processing system for controlling execution of a debug function and method therefor. Motorola, John Gustav Larson, Michael P Noonan, March 7, 2000: US06035422 (48 worldwide citation)

A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) ...