1
Joseph Andrew Iadanza: System and method for dynamically reconfiguring a programmable gate array. International Business Machines Corporation, Susan M Murray Esq, Heslin & Rothenberg P C, July 8, 1997: US05646544 (309 worldwide citation)

In each of multiple logic cells of a Programmable Gate Array ("PGA"), a programing array is provided having multiple programming words therein. Each of the programming words is engagable to control the configuration of the logic cell. The programming words are selectively engaged such that multiple ...


2
Joseph Andrew Iadanza, Frank Ray Keyser III: Programmable bit line drive modes for memory arrays. International Business Machines Corporation, Heslin & Rothenberg P C, March 28, 2000: US06044031 (142 worldwide citation)

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo ...


3
Joseph Andrew Iadanza, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch: Field programmable memory array. International Business Machines Corporation, Heslin & Rothenberg P C, June 22, 1999: US05914906 (141 worldwide citation)

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo ...


4
Kim P N Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch: Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array. International Business Machines Corporation, Heslin & Rothenberg P C, February 8, 2000: US06023421 (139 worldwide citation)

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo ...


5
Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser III, Terrance John Zittritsch: Programmable address decoder for field programmable memory array. International Business Machines Corporation, Heslin & Rothenberg P C, October 10, 2000: US06130854 (138 worldwide citation)

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo ...


6
Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser III, Victor Paul Seidel, Terrance John Zittritsch: Field programmable memory array. International Business Machines Corporation, Tiffany Townsend Esq, Heslin & Rothenberg P C, June 13, 2000: US06075745 (132 worldwide citation)

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo ...


7
Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser III: Field programmable memory array. International Business Machines Corporation, Heslin & Rothenberg P C, May 15, 2001: US06233191 (131 worldwide citation)

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo ...


8
Joseph Andrew Iadanza, Frank Ray Keyser III, Ralph David Kilmoyer, Michael Joseph Laramie: System for implementing write, initialization, and reset in a memory array using a single cell write port. International Business Machines Corporation, Heslin & Rothenberg P C, September 1, 1998: US05802003 (129 worldwide citation)

A system is provided for providing functional, initialization and reset access to a plurality of memory cells of a memory array, using a single cell write port and a single cell read port. In addition to functional address and data buses, initialization address and data buses are provided. The inven ...


9
Joseph Andrew Iadanza: Programmable read ports and write ports for I/O buses in a field programmable memory array. International Business Machines Corporation, Heslin & Rothenberg P C, July 18, 2000: US06091645 (128 worldwide citation)

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo ...


10
Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser III, Terrance John Zittritsch: Method of operating a field programmable memory array with a field programmable gate array. International Business Machines Corporation, Tiffany Townsend Esq, Heslin & Rothenberg P C, September 12, 2000: US06118707 (128 worldwide citation)

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo ...