1
Paul J Wodarczyk, Frederick P Jones, John M S Neilson, Joseph A Yedinak: Power MOSFET transistor circuit with active clamp. Harris Corporation, Kenneth Watov, January 7, 1992: US05079608 (105 worldwide citation)

A power MOS transistor, including source, drain, and gate electrodes, comprises a substrate of a semiconductor material of one conductivity type having first and second opposed surfaces; a drain region extending through the substrate between the surfaces; a plurality of spaced body regions of the op ...


2
Frederick P Jones, Joseph A Yedinak, John M S Neilson, Robert S Wrathall, Jeffrey G Mansmann, Claire E Jackoski: Power VDMOSFET with schottky on lightly doped drain of lateral driver FET. Harris Corporation, Watov & Kipnes, November 17, 1992: US05164802 (80 worldwide citation)

A monolithic semiconductor device comprises a VDMOS transistor having first and second main electrodes and a control electrode, and a lateral MOSFET having first and second main electrodes and a control electrode, wherein one of the first and second electrodes of the lateral MOSFET has a lower dopin ...


3
Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P Sapp, Dean E Probst, Nathan L Kraft, Thomas E Grebs, Rodney S Ridley, Gary M Dolny, Bruce D Marchant, Joseph A Yedinak: Trench-gate field effect transistors and methods of forming the same. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, March 17, 2009: US07504303 (52 worldwide citation)

A method for forming a shielded gate field effect transistor includes the following steps. Trenches extending into a silicon region are formed using a mask that includes a protective layer. A shield dielectric layer lining sidewalls and bottom of each trench is formed. A shield electrode is formed i ...


4
John M S Neilson, Frederick P Jones, Joseph A Yedinak, Christopher L Rexer: Power FET with gate segments covering drain regions disposed in a hexagonal pattern. Harris Corporation, Spensley Horn Jubas & Lubitz, June 21, 1994: US05323036 (34 worldwide citation)

In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, ...


5
Chanho Park, Joseph A Yedinak, Christopher Boguslaw Kocon, Jason Higgs, Jaegil Lee: Periphery design for charge balance power devices. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, September 29, 2009: US07595542 (23 worldwide citation)

A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes ...


6
Joseph A Yedinak, Jack E Wojslawowicz, Bernard J Czeck, Robert D Baran, Douglas Lange: Thick buffer region design to improve IGBT self-clamped inductive switching (SCIS) energy density and device manufacturability. Fairchild Semiconductor Corporation, Thomas R FitzGerald Esq, August 17, 2004: US06777747 (22 worldwide citation)

An IGBT has a thick buffer region with increased doping to improve self-clamped inductive switching and device manufacture. A planar or trench gate IGBT has a buffer layer more than 25 microns thick. The buffer layer is doped high enough so that its carriers are more numerous than minority carriers, ...


7
Nathan L Kraft, Ashok Challa, Steven P Sapp, Hamza Yilmaz, Daniel Calafut, Dean E Probst, Rodney S Ridley, Thomas E Grebs, Christopher B Kocon, Joseph A Yedinak, Gary M Dolny: Trench FET with improved body to gate alignment. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, August 26, 2008: US07416948 (21 worldwide citation)

A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor re ...


8
Joseph A Yedinak, Dwayne S Reichl, Douglas J Lange: Method of isolating the current sense on power devices while maintaining a continuous stripe cell. Fairchild Semiconductor Corporation, Thomas R FitzGerald Esq, Hiscock & Barclay, October 10, 2006: US07118951 (20 worldwide citation)

An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body st ...


9
Joseph A Yedinak, Ashok Challa: Trench-based power semiconductor devices with increased breakdown voltage characteristics. Fairchild Semiconductor Corporation, November 6, 2012: US08304829 (17 worldwide citation)

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.


10
Joseph A Yedinak, Jon Gladish, Sampat Shekhawat, Gary M Dolny, Praveen Muraleedharan Shenoy, Douglas Joseph Lange, Mark L Rinehimer: Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off. Fairchild Semiconductor Corporation, Thomas R FitzGerald Esq, Laurence S Roach Esq, December 14, 2004: US06831329 (16 worldwide citation)

A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitan ...