1
Jung Herng Chang, Curt Berg, Jorge Cruz Rios: Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, March 14, 1995: US05398325 (78 worldwide citation)

Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a small internal cache memory structure. A subs ...


2
Pradeep S Sindhu, Bjorn Liencres, Jorge Cruz Rios, Douglas B Lee, Jung Herng Chang, Jean Marc Frailong: Apparatus and method for a synchronous, high speed, packet-switched bus. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, March 16, 1993: US05195089 (54 worldwide citation)

A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher cl ...


3
Jung Herng Chang, Curt Berg, Jorge Cruz Rios: Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, December 27, 1994: US05377345 (27 worldwide citation)

Apparatus and methods for a cache controller preserving cache consistency and providing multiple outstanding operations in a cache memory structure supporting a high performance central processor unit (CPU). An external cache array is coupled to both the CPU and a cache controller (CC), and is subbl ...


4
Song Zhang, Jorge Cruz Rios, Anurag P Gupta: Systems and methods for limiting low priority traffic from blocking high priority traffic. Juniper Networks, Harrity Snyder, October 10, 2006: US07120113 (26 worldwide citation)

A method for processing high priority packets and low priority packets in a network device includes performing arbitration on high priority packets until no high priority packets remain. Arbitration then is enabled on low priority packets. A packet size associated with the selected low priority pack ...


5
Sreeram Veeragandham, Rami Rahim, Song Zhang, Anurag P Gupta, Jorge Cruz Rios, Jayabharat Boddu, Jeffrey R Zimmer, Jia Chang Wang, Srihari Shoroff, Chi Chung K Chen: Systems and methods for improving packet scheduling accuracy. Juniper Networks, Harrity & Harrity, June 30, 2009: US07554919 (7 worldwide citation)

A packet scheduler is configured to perform quality of service (QoS) scheduling on a per-data unit basis. A downstream processing engine is operatively connected to the packet scheduler for receiving forwarded packets. A feedback path is operatively connected between the downstream processing engine ...


6
Song Zhang, Jorge Cruz Rios, Anurag P Gupta: Systems and methods for limiting low priority traffic from blocking high priority traffic. Juniper Networks, Harrity & Harrity, November 30, 2010: US07843816 (3 worldwide citation)

A method for processing high priority packets and low priority packets in a network device includes performing arbitration on high priority packets until no high priority packets remain. Arbitration then is enabled on low priority packets. A packet size associated with the selected low priority pack ...


7
Song Zhang, Jorge Cruz Rios, Anurag P Gupta: Systems and methods for limiting low priority traffic from blocking high priority traffic. Juniper Networks, Harrity Snyder, March 18, 2008: US07346001 (2 worldwide citation)

A method for processing high priority packets and low priority packets in a network device includes performing arbitration on high priority packets until no high priority packets remain. Arbitration then is enabled on low priority packets. A packet size associated with the selected low priority pack ...


8
Sreeram Veeragandham, Rami Rahim, Song Zhang, Anurag P Gupta, Jorge Cruz Rios, Jayabharat Boddu, Jeffrey R Zimmer, Jia Chang Wang, Srihari Shoroff, Chi Chung K Chen: Systems and methods for improving packet scheduling accuracy. Juniper Networks, Harrity & Harrity, July 12, 2011: US07978609 (2 worldwide citation)

A packet scheduler is configured to perform quality of service (QoS) scheduling on a per-data unit basis. A downstream processing engine is operatively connected to the packet scheduler for receiving forwarded packets. A feedback path is operatively connected between the downstream processing engine ...


9
Jorge Cruz Rios, Rami Rahim, Venkateswarlu Talapaneni, Pradeep Sindhu: Memory allocation using a memory address pool. Juniper Networks, Harrity Snyder, May 2, 2006: US07039774 (2 worldwide citation)

A system for managing memory includes a memory and a memory allocation unit. The memory stores a pool of memory addresses for writing data to the memory and stores a counter value. The memory allocation unit retrieves memory addresses from the pool in response to write requests from data sources. Th ...


10
Song Zhang, Anurag P Gupta, Raymond Lim, Jorge Cruz Rios, Phil Lacroute: Systems and methods for processing packet streams in a network device. Juniper Networks, Harrity & Snyder, October 21, 2003: US06636952 (2 worldwide citation)

A network device includes systems and methods for processes streams of data. The network device stores data and addresses corresponding to the streams in a memory. The addresses store pointers to the data. Output logic within the network device determines whether an address is required to be fetched ...