1
Joo Weon Park, Kyung Joon Han, Gyu Wan Kwon, Jong Seuk Lee: Virtual ground nonvolatile semiconductor memory array architecture and integrated circuit structure therefor. NexFlash Technologies, Altera Law Group, November 30, 2004: US06826080 (54 worldwide citation)

In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or t ...


2
Robin J Jigour, Eungjoon Park, Joo Weon Park, Jong Seuk Lee: Serial flash semiconductor memory. Winbound Electronics Corporation, Cyr & Associates P A, July 7, 2009: US07558900 (43 worldwide citation)

A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial ...


3
Kyung Joon Han, Steve K Hsia, Joo Weon Park, Gyu Wan Kwon, Jong Seuk Lee: Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof. NexFlash Technologies, Altera Law Group, March 29, 2005: US06873004 (20 worldwide citation)

An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in ...


4
Joo Weon Park, Poongyeub Lee: Nonvolatile memory integrated circuit having volatile utility and buffer memories, and method of operation thereof. NexFlash Technologies, Altera Law Group, August 10, 2004: US06775184 (20 worldwide citation)

A memory integrated circuit includes a nonvolatile memory array that is programmed in page mode. A volatile utility memory is connected to the memory array, and is at least a page in size so that an entire page of data that is either being programmed into or read from the memory array may be stored ...


5
Young Jung Choi, Joo Weon Park: Flash memory device. Hyudai Electronics, Fish & Richardson P C, July 7, 1998: US05777922 (16 worldwide citation)

The present invention provides a flash memory device wherein memory cells in each of the memory cell blocks are divided into a plurality of memory cell groups. In each memory cell group, local bit lines are laid out connected by segmentation transistors. When selecting a memory cell, only a local bi ...


6
Joo Weon Park, Poongyeub Lee, Eungjoon Park, Kyung Joon Han: Nonvolatile memory having bit line discharge, and method of operation thereof. NexFlash Technologies, Altera Law Group, June 21, 2005: US06909639 (15 worldwide citation)

The problem of bit disturb is reduced by discharging the floating bit lines of a nonvolatile memory array during programming. An illustrative virtual ground memory array uses single transistor floating gate type memory cells that are programmed using Fowler-Nordheim (“FN”) tunneling, highly conducti ...


7
Joo Weon Park: Flash memory device. Hyundai Electronics, Fish & Richardson P C, December 2, 1997: US05694359 (13 worldwide citation)

The present invention relates to a flash memory cell device having a repair circuit for replacing a fail cell of main memory cell arrays with a spare cell. The flash memory device according to the present invention comprises a main memory cell array, a redundancy cell block, a redundancy row decoder ...


8
Young Jung Choi, Joo Weon Park: Negative voltage drive circuit. Hyundai Electronic, Scott C Harris Esq, July 6, 1999: US05920225 (10 worldwide citation)

The present invention discloses a negative voltage drive circuit which does not takes an influence from the load capacitor or the power supply voltage drive circuit according to the present invention comprises a cross pumping circuit, a pumping unit block and circuit for supplying VCC or VSS power s ...


9
Joo Weon Park, Hyung Rae Park: Method of erasing a flash memory cell and device for erasing the same. Hyundai Electronics, Scott C Harris Esq, October 5, 1999: US05963479 (6 worldwide citation)

The present invention disclosed a method of erasing a flash memory comprising the step of applying a drain bias voltage for erasing to any one of said sectors; applying a drain bias voltage for erasing to a next sector before said sector is completely erased, whereby the sectors are erased sequentia ...


10
Poongyeub Lee, Joo Weon Park, Kwangho Kim, Eungjoon Park: Nonvolatile memory and method of operation thereof to control erase disturb. NexFlash Technologies, Altera Law Group, July 27, 2004: US06768671 (6 worldwide citation)

In an array of nonvolatile memory cells, as many memory cells as desired and indeed even the entire array of memory cells may be placed in a single region of the bulk, illustratively a p-well. Peripheral circuitry is used to in effect section the memory array into blocks and groups of blocks, and to ...