1
John Sudijono, Liang Ch O Hsia, Liu Wu Ping: Copper recess formation using chemical process for fabricating barrier cap for lines and vias. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, Stephen G Stanton, March 16, 2004: US06706625 (93 worldwide citation)

A method of fabricating a planarized barrier cap layer over a metal structure comprising the following steps. A substrate having an opening formed therein is provided. The substrate having an upper surface. A planarized metal structure is formed within the opening. The planarized metal structure bei ...


2
John Sudijono, Liang Choo Hsia, Liu Huang: Use of amorphous carbon as a removable ARC material for dual damascene fabrication. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, September 7, 2004: US06787452 (33 worldwide citation)

An improved method of controlling a critical dimension during a photoresist patterning process is provided which can be applied to forming vias and trenches in a dual damascene structure. An amorphous carbon ARC is deposited on a substrate by a PECVD method. Preferred conditions are a RF power from ...


3
Huang Liu, John Sudijono, Charles Lin, Quah Ya Lin: Two-step, low argon, HDP CVD oxide deposition process. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, April 3, 2001: US06211040 (29 worldwide citation)

A method for depositing silicon dioxide between features has been achieved. The method may be applied intermetal dielectrics, interlevel dielectric, or shallow trench isolations. This method prevents dielectric voids, corner clipping, and plasma induced damage in very small feature applications. Fea ...


4
Boon Meng Seah, Bei Chao Zhang, Raymond Joy, Shao Beng Law, John Sudijono, Liang Choo Hsia: Apparatus and methods for cleaning and drying of wafers. GLOBALFOUNDRIES Singapore, Horizon IP, May 15, 2012: US08177993 (22 worldwide citation)

An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas ...


5
Johnny Widodo, Bei Chao Zhang, Tong Qing Chen, Yong Kong Siew, Fan Zhang, San Leong Liew, John Sudijono, Liang Choo Hsia: Entire encapsulation of Cu interconnects using self-aligned CuSiN film. Chartered Semiconductor Manufacturing, Horizon IP, April 28, 2009: US07524755 (22 worldwide citation)

A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer ...


6
Khee Yong Lim, Wenhe Lin, Chung Woh Lai, Yong Meng Lee, Liang Choo Hsia, Young Way Teh, John Sudijono, Wee Leng Tan, Hui Peng Koh: Composite stress spacer. Chartered Semiconductor Manufacturing, William J Stoffel, August 14, 2007: US07256084 (12 worldwide citation)

An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The ...


7
Liu Huang, John Sudijono, Koh Yee Wee: Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication. Chartered Semiconductor Manufacturing, George D Saile, Rosemary L S Pike, Stephen B Ackerman, May 30, 2006: US07052932 (11 worldwide citation)

A method of forming a dual damascene structure with improved performance is described. A first etch stop layer comprised of oxygen doped SiC is deposited on a SiC barrier layer to form a composite barrier/etch stop layer on a substrate. The remainder of the damascene stack is formed by sequentially ...


8
Young Way Teh, Yong Meng Lee, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, John Sudijono, Hui Peng Koh, Liang Choo Hsia: Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS. Chartered Semiconductor Manufacturing, Horizon IP, November 4, 2008: US07445978 (11 worldwide citation)

An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is ...


9
Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Xu Yi: Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, Stephen G Stanton, January 22, 2002: US06340608 (11 worldwide citation)

A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump ...


10
Liu Huang, John Sudijono: Deposition and sputter etch approach to extend the gap fill capability of HDP CVD process to ≦0.10 microns. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, March 29, 2005: US06872633 (7 worldwide citation)

A method of filling an STI feature with a dielectric material using a HDP CVD technique is described. By omitting an inert carrier gas like argon in the first CVD step, a small keyhole in a SiO2 layer is formed near the top of the trench. A sputter etch step in the same CVD chamber then removes diel ...



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