1
Edward Grochowski, John Shen, Hong Wang, Doron Orenstein, Gad S Sheaffer, Ronny Ronen, Murali M Annavaram: Method and apparatus for varying energy per instruction according to the amount of available parallelism. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 14, 2008: US07437581 (70 worldwide citation)

A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the va ...


2
Quinn A Jacobson, Hong Wang, John Shen, Gautham N Chinya, Per Hammarlund, Xiang Zou, Bryant Bigbee, Shivnandan D Kaushik: Primitives to enhance thread-level speculation. Intel Corporation, David P McAbee, February 1, 2011: US07882339 (27 worldwide citation)

A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an ...


3
Ryan Rakvic, Richard A Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K Poulsen, Sanjiv Shah, John Shen, Gautham Chinya: Load balancing for multi-threaded applications via asymmetric power throttling. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 31, 2012: US08108863 (24 worldwide citation)

A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to t ...


4
Hong Wang, Hong Jiang, John Shen, Porus S Khajotia, Ming W Choy, Narayan Biswal: Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resource. Intel Corporation, Trop Pruner & Hu P C, February 3, 2009: US07487341 (22 worldwide citation)

In one embodiment, the present invention includes a method for communicating a request for handling of a fault or exception occurring in an accelerator to a first instruction sequencer coupled thereto. The accelerator may be a heterogeneous resource with respect to the first instruction sequencer, e ...


5
Natalie D Enright, Jamison D Collins, Perry Wang, Hong Wang, Xinmin Tran, John Shen, Gad Sheaffer, Per Hammarlund: Mechanism to exploit synchronization overhead to improve multithreaded performance. Intel Corporation, David P McAbee, September 8, 2009: US07587584 (18 worldwide citation)

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and an event detector to detect a long latency event associated with a synchroniza ...


6
Zheng John Shen: Power MOSFET. Great Wall Semiconductor Corporation, Goodwin Procter, December 6, 2005: US06972464 (18 worldwide citation)

A system of interconnecting regions on an integrated semiconductor device or discrete components. As first connectivity layer has first and second runners to interconnect a plurality of first and second regions. A second connectivity layer has third runners to interconnect the first runners and four ...


7
Hong Wang, Perry Wang, Ralph Kling, Neil A Chazin, John Shen: Quantization and compression for computation reuse. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, June 27, 2006: US07069545 (17 worldwide citation)

Software reuse instances are found from an execution trace through a process of quantization, discovery, and synthesis. Quantization includes mapping n-dimensional vectors that correspond to instructions, live-in states, and live-out states to one dimensional symbols, and arranging the symbols into ...


8
Xinmin Tian, Milind Girkar, David C Sehr, Richard Grove, Wei Li, Hong Wang, Chris Newburn, Perry Wang, John Shen: Thread-data affinity optimization using compiler. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 11, 2011: US08037465 (14 worldwide citation)

Thread-data affinity optimization can be performed by a compiler during the compiling of a computer program to be executed on a cache coherent non-uniform memory access (cc-NUMA) platform. In one embodiment, the present invention includes receiving a program to be compiled. The received program is t ...


9
Gautham N Chinya, Hong Wang, Xiang Zou, James Paul Held, Prashant Sethi, Trung Diep, Anil Aggarwal, Baiju V Patel, Shiv Kaushik, Bryant Bigbee, John Shen, Richard A Hankins, John L Reid: Mechanism to emulate user-level multithreading on an OS-sequestered sequencer. Intel Corporation, Caven & Aghevli, October 5, 2010: US07810083 (13 worldwide citation)

Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the a ...


10
Hong Wang, Tor Aamodt, Per Hammarlund, John Shen, Xinmin Tian, Milind Girkar, Perry Wang, Steve Shih wei Liao: Safe store for speculative helper threads. Intel Corporation, David P McAbee, February 2, 2010: US07657880 (13 worldwide citation)

The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is permitted to execute Store instructions. Store blocker logic operates to prevent data associated with a Store instruction in a helper ...