1
John S Fernando, Stefan Thurnhofer: Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths. Agere Systems Guardian, Synnestvedt & Lechner, August 7, 2001: US06272616 (207 worldwide citation)

A parallel processing architecture for a digital processor capable of alternately operating in a single threaded mode, a SIMD (single instruction, multiple data) mode and a MIMD (multiple instructions, multiple data) mode. The instruction set for the processor includes instructions for switching bet ...


2
Sanjay S Mathur, John S Fernando: Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors. Unisys Corporation, Alfred W Kozak, Mark T Starr, June 18, 1991: US05025365 (99 worldwide citation)

This disclosure describes a snooping coherency protocol for a multiprocessor network wherein every processor has its own private cache and bus interface means and the network is connected via a common system bus. Each processor has its own cache directory and image directory that duplicate each othe ...


3
Michael R Betker, John S Fernando, Frank Lemmon, Shaun P Whalen: Pointer register indirectly addressing a second register in the processor core of a digital processor. Lucent Technologies, April 18, 2000: US06052766 (31 worldwide citation)

A first register stores a value that can be used as a pointer to indirectly address a second register. The first register is referred to as a pointer register and the pointer as a register pointer. The second register may be a conventional register that stores a conventional register value (i.e., a ...


4
John S Fernando, Frank T Lemmon, Shaun P Whalen: Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously. Agere Systems Guardian, Dickstein Shapiro Morin & Oshinsky, July 31, 2001: US06269440 (20 worldwide citation)

An apparatus and method that speeds the processing of data vectors in a digital processor is disclosed. In accordance with the present invention, a vector zero overhead loop with parallel issue processes multiple data elements at the same time, and yet is programmed with readable assembly language a ...


5
Ramesh V Peri, John S Fernando, Ravi Kolagotla, Srinivas P Doddapaneni: Accessing data from different memory locations in the same cycle. Intel Corporation, Trop Pruner & Hu P C, May 12, 2009: US07533232

In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing bot ...


6
Harry Dwyer, John S Fernando: Method and apparatus for adaptive cache frame locking and unlocking. Agere Systems, Ryan Mason & Lewis, July 2, 2013: US08478944

Most recently accessed frames are locked in a cache memory. The most recently accessed frames are likely to be accessed by a task again in the near future and may be locked at the beginning of a task switch or interrupt to improve cache performance. The list of most recently used frames is updated a ...


7
Ramesh V Peri, John S Fernando, Ravi Kolagotla, Srinivas P Doddapaneni: Accessing data from different memory locations in the same cycle. Trop Pruner & Hu PC, May 19, 2005: US20050108493-A1

In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing bot ...