1
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing computer with overlapping windows-div. Visual Information Technologies, Baker & Botts, September 8, 1992: US05146592 (206 worldwide citation)

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addre ...


2
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing system using separate data processor and address generator. Visual Information Technologies, Baker & Botts, January 15, 1991: US04985848 (200 worldwide citation)

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addre ...


3
John P Norsworthy, Jay A Thompson: Internet transaction acceleration. Microtune, Fulbright & Jaworski L, November 7, 2000: US06144402 (108 worldwide citation)

The invention is a multiple mode transmission system that interconnects the computer of a user with the Internet. The system has a first link that is a relatively low bandwidth telephone system. The system also has a second link that is a relatively high bandwidth television system. The television l ...


4
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing computer. Visual Information Technologies, Baker & Botts, July 7, 1992: US05129060 (40 worldwide citation)

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addre ...


5
John P Norsworthy, Stanley Vincent Birleson, Douglas J Bartek: System and method for providing fast acquire time tuning of multiple signals to present multiple simultaneous images. Microtune, Fulbright & Jaworski, August 31, 2004: US06784945 (34 worldwide citation)

A multiple information decoding system and method are provided in which multiple information content is decoded sequentially and provided to a viewer such that the viewer perceives the information content as being simultaneously decoded. One embodiment of the system and method is in a video display ...


6
John P Norsworthy: DAC achieving monotonicity with equal sources and shift array therefor. Cirrus Logic, Fulbright & Jaworski, July 23, 1996: US05539405 (32 worldwide citation)

Disclosed is a system and method for providing full monotonicity among desired sequential output values by converting a stream of sequential input signals each of which are representative of their corresponding desired output values. The disclosed invention comprises a system and method for individu ...


7
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing computer. Visual Information Technologies, Baker & Botts, April 28, 1992: US05109348 (31 worldwide citation)

Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives ...


8
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing computer with error correction and logging. Visual Information Technologies, Baker Mills & Glast, September 4, 1990: US04955024 (23 worldwide citation)

Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives ...


9
Allan H Dansky, John P Norsworthy: High speed low power current controlled gate circuit. IBM Corporation, John F Ohlandt, August 12, 1986: US04605870 (20 worldwide citation)

The invention pertains to semiconductor circuitry, and more particularly to a class of circuitry known as current controlled gate circuits for driving very large scale integrated circuit gate arrays; the novel circuit can achieve much lower speed-power products than other circuitry, such as the well ...


10
John P Norsworthy, David T Stoner, Michael K Corry: Memory controller flexible timing control system and method. Pixel Semiconductor, Baker & Botts, January 4, 1994: US05276856 (17 worldwide citation)

There is disclosed a system and method of controlling the timing in a system having a number of different elements, each requiring individual timing signals. The system utilizes a RAM memory divided into a number of groups or cycle types, each cycle type having a number of addressable words. The ind ...