1
Bryan Black, Murali M Annavaram, Donald W McCauley, John P Devale: Prefetching from dynamic random access memory to a static random access memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 4, 2011: US08032711 (37 worldwide citation)

Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch l ...


2
Mohammed H Taufique, Derwin Jallice, Donald W McCauley, John P DeVale, Edward A Brekelbaum, Jeffrey P Rupley II, Gabriel H Loh, Bryan Black: Memory array on more than one die. Intel Corporation, Matthew C Fagan, April 6, 2010: US07692946 (3 worldwide citation)

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital sign ...


3
John P DeVale, Bryan P Black, Edward A Brekelbaum, Jeffrey P Rupley II: Multi-purpose register cache. Intel Corporation, Erik M Metzger, August 26, 2008: US07418551 (3 worldwide citation)

A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.


4
Mohammed H Taufique, Derwin Jallice, Donald W McCauley, John P DeVale, Edward A Brekelbaum, Jeffrey P Rupley II, Gabriel H Loh, Bryan Black: Memory array on more than one die. Intel Corporation, Guojun Zhou, November 15, 2011: US08059441 (2 worldwide citation)

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital sign ...


5
John P Devale, Bryan P Black, Edward A Brekelbaum, Jeffrey P Rupley II: Predictive filtering of register cache entry. Intel Corporation, Shireen I Bacon, January 30, 2007: US07171545 (2 worldwide citation)

A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.


6
Bryan Black, Murali M Annavaram, Donald W McCauley, John P Devale: Prefetching from dynamic random access memory to a static random access memory. Intel Corporation, Intel Corporation, c o INTELLEVATE, June 26, 2008: US20080155196-A1

Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch l ...


7
Mohammed H Taufique, Derwin Jallice, Donald W McCauley, John P DeVale, Jeffrey P Rupley II, Edward A Brekelbaum, Gabriel H Loh, Bryan Black: Memory array on more than one die. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 1, 2009: US20090001601-A1

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital sign ...


8
John P Devale, Bryan P Black, Edward A Brekelbaum, Jeffrey P Rupley: Predictive filtering of register cache entry. Intel Corporation, Venable, July 7, 2005: US20050149681-A1

A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.


9
John P DeVale, Bryan P Black, Edward A Brekelbaum, Jeffrey P Rupley: Multi-purpose register cache. Blakely Sokoloff Taylor & Zafman, January 12, 2006: US20060010292-A1

A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.


10
Mohammed Taufique, Derwin Jallice, Donald W McCauley, John P DeVale, Edward A Brekelbaum, Jeffrey P Rupley II, Gabriel H Loh, Bryan Black: Memory array on more than one die. Intel Bstz, Blakely Sokoloff Taylor & Zafman, June 17, 2010: US20100149849-A1

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital sign ...