1
Robert P Colwell, John O Donnell, David B Papworth, Paul K Rodman: Hierarchical priority branch handling for parallel execution in a parallel processor. Multiflow Computer, Hale and Dorr, May 23, 1989: US04833599 (207 worldwide citation)

In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority syste ...


2
Robert P Colwell, John O Donnell, David B Papworth, Paul K Rodman: Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus. Digital Equipment Corporation, Denis G Maloney, Barry Young, Ron Myrick, January 12, 1993: US05179680 (107 worldwide citation)

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the ...


3
Robert P Colwell, John O Donnell, David B Papworth, Paul K Rodman: Instruction storage method with a compressed format using a mask word. Digital Equipment Corporation, Finnegan Henderson Farabow Garrett and Dunner, October 15, 1991: US05057837 (98 worldwide citation)

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the ...


4
Robert P Colwell, John O Donnell, David B Papworth, Paul K Rodman: Virtual address table look aside buffer miss recovery method and apparatus. Multiflow Computer, Hale and Dorr, April 24, 1990: US04920477 (84 worldwide citation)

A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condi ...


5
John O Donnell: System and method for managing energy generation equipment. DTE Energy Technologies, Williams Mullen P C, Thomas F Bergert, December 25, 2007: US07313465 (79 worldwide citation)

A system and method for controlling distributed generation equipment based on remotely derived dispatch schemes improves economics and reliability of operation. The system can adapt to variable changing conditions in real-time to provide adaptable, real-time, site-specific load forecasting. The pres ...


6
John O Donnell, Cameron D Sherding: System and method for managing energy generation equipment. DTE Energy Technologies, Williams Mullen, Thomas F Bergert, October 24, 2006: US07127327 (51 worldwide citation)

A system and method for controlling distributed generation equipment based on remotely derived dispatch schemes improves economics and reliability of operation. The system can adapt to variable changing conditions in real-time to provide adaptable, real-time, site-specific load forecasting.


7
David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O Donnell, John Poole legal representative, Ashok Raman, Eric Rehm, Radhika Thekkath: Data streamer. Hitachi, Equator Technologies, Sofer & Haroun, June 16, 2009: US07548996 (29 worldwide citation)

In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus ar ...


8
Robert P Colwell, John O Donnell, David B Papworth, Paul K Rodman: High bandwidth multiple computer bus apparatus. Digital Equipment Corporation, Denis Cefalo Albert P Maloney, April 26, 1994: US05307506 (26 worldwide citation)

A parallel processor has a plurality of communication buses advantageously interconnecting the arithmetic processor elements, the memory controller elements, a global controller circuitry, and input/output processors. The processor preferably has at least one central processing unit cluster, the clu ...


9
David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O Donnell, Ashok Raman, Eric Rehm, Radhika Thekkath: Data transfer engine of a processor having a plurality of modules. Hitachi, Equator Technologies, Sofer&Haroun, May 23, 2006: US07051123 (21 worldwide citation)

In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus ar ...


10
Michael D Carr, Maurice G Perini, John O Donnell, Anthony B Leaning, Anthony R Leaning: Signal coding. British Telecommunications public company, Nixon & Vanderhye, April 16, 1991: US05008748 (15 worldwide citation)

The present invention relates to signal coding, and particularly, though not exclusively, to coding of video signals, especially using conditional replenishment coding, where information is transmitted only in respect of elements of a frame of the picture which have changed relative to the previous ...