1
Ravi Kumar Arimilli, John Michael Kaiser: Queued arbitration mechanism for data processing system. International Business Machines Corporation, Kelly K Winstead Sechrest & Minick P C Kordzik, Anthony V S England, February 22, 2000: US06029217 (75 worldwide citation)

A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus util ...


2
John Michael Kaiser, Warren Edward Maule, David Wayne Victor: Information handling system including non-disruptive command and data movement between storage and one or more auxiliary processors. International Business Machines Corporation, George E Clark, Leslie A Van Leeuwen, May 1, 2001: US06226695 (24 worldwide citation)

An information handling system which efficiently processes auxiliary functions such as graphics processing includes one or more processors, a high speed processor bus connecting the one or more processors, a memory controller for controlling memory and for controlling the auxiliary function processi ...


3
Ravi Kumar Arimilli, John Steven Dodson, John Michael Kaiser, Jerry Don Lewis: Cache intervention from a cache line exclusively holding an unmodified value. International Business Machines Corporation, Richard A Henkler, Jack V Musgrove, Andrew J Dillon, October 5, 1999: US05963974 (20 worldwide citation)

A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a cache, the cache is marked as containing an exclusively held, unmodified copy of the value and, when a ...


4
John Michael Kaiser, Warren Edward Maule, Robert Dominick Mirabella, David Wayne Victor: Method and apparatus for data ordering of I/O transfers in Bi-modal Endian PowerPC systems. International Business Machines Corporation, Kelly K Winstead Sechrest & Minick P C Kordzik, April 27, 1999: US05898896 (19 worldwide citation)

To present a consistent image of storage facilities to components in Bi-modal Endian PowerPC system enviromnents, provision is made for transferring data between system components in the appropriate Endian format. Endian conversion function can be incorporated into the memory controller subsystem by ...


5
Sanjay Raghunath Deshpande, John Michael Kaiser: Method and apparatus for coherency reporting in a multiprocessing system. International Business Machines Corporation, Anthony V S England, September 30, 1997: US05673413 (19 worldwide citation)

An information processing system includes a plurality of bus devices coupled to at least one storage device via a bus. A first device (the "requestor") on a bus issues a request to obtain data and coherency information and monitors for the coherency information during a designated coherency response ...


6
Ravi Kumar Arimilli, John Steven Dodson, John Michael Kaiser, Jerry Don Lewis: Cache intervention from only one of many cache lines sharing an unmodified value. International Business Machines Corporation, Richard A Henkler, Jack V Musgrove, Andrew J Dillon, August 17, 1999: US05940856 (15 worldwide citation)

A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the value and, when ...


7
John Michael Kaiser, Warren Edward Maule, Robert George Schaaf, David Wayne Victor: System for transferring data from a source device to a target device in which the address of data movement engine is determined. International Business Machines Corporation, Kelly K Winstead Sechrest & Minick P C Kordzik, Anthony V S England, June 9, 1998: US05765022 (15 worldwide citation)

PowerPC external control instructions are utilized to pass a translated address to a transfer engine located in the system memory controller, together with previously transferred parameters into control registers within the memory controller. An accelerated data movement is accomplished between syst ...


8
Ravi Kumar Arimilli, John Michael Kaiser, Warren Edward Maule: Handling interrupts by returning and requeuing currently executing interrupts for later resubmission when the currently executing interrupts are of lower priority than newly generated pending interrupts. International Business Machines Corporation, Russell D Culbertson, Anthony V S England, May 9, 2000: US06061757 (14 worldwide citation)

An information handling system includes one or more processing units, a data management unit, connected to the processor data bus, to a memory system, and to an I/O bus, an address management unit, connected to the processor address bus, to the memory system, and to an I/O bus. Data management unit ...


9
Ravi Kumar Arimilli, John Steven Dodson, John Michael Kaiser, Jerry Don Lewis: Method of shared intervention via a single data provider among shared caches for SMP bus. International Business Machines Corporation, Richard A Henkler, Jack V Musgrove, Andrew J Dillion, August 24, 1999: US05943685 (13 worldwide citation)

A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. A requesting processing unit issues a message to an interconnect of the computer system indicating that the requesting processing unit desires to read a value from an address ...


10
Ravi Kumar Arimilli, John Steven Dodson, John Michael Kaiser, Jerry Don Lewis: Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing. International Business Machines Corporation, Richard A Henkler, Jack V Musgrove, Andrew J Dillon, August 31, 1999: US05946709 (11 worldwide citation)

A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a plurality of caches, one cache is identified as a specific cache which contains an unmodified copy of t ...