1
John Michael Borkenhagen, William Thomas Flynn, Andrew Henry Wottreng: Altering thread priorities in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, April 3, 2001: US06212544 (273 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


2
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Sheldon Bernard Levenstein, Andrew Henry Wottreng: Thread switch control in a multithreaded processor system. International Business Machines Corporation, Karuna Ojanen, May 20, 2003: US06567839 (208 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


3
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Andrew Henry Wottreng: Method and apparatus to force a thread switch in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, June 13, 2000: US06076157 (177 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


4
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Andrew Henry Wottreng: Method and apparatus for selecting thread switch events in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, February 24, 2004: US06697935 (147 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


5
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Steven R Kunkel, Sheldon Bernard Levenstein, Andrew Henry Wottreng: Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, Birch Stewart Kolasch & Birch, August 15, 2000: US06105051 (69 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


6
John Michael Borkenhagen, Todd Alan Greenfield: Method and apparatus for implementing high speed DDR SDRAM read interface with reduced ACLV effects. International Business Machines Corporation, Joan Pennington, August 27, 2002: US06442102 (42 worldwide citation)

A method and apparatus are provided for implementing high speed double data rate (DDR) synchronous dynamic random access memory (SDRAM) read interface with reduced across chip line-width variation (ACLV) effects. A delay circuit is utilized for providing a delay output. A calibration clock input is ...


7
John Michael Borkenhagen, Brian T Vanderpool: SDRAM address error detection method and apparatus. International Business Machines Corporation, Joan Pennington, June 22, 2004: US06754858 (40 worldwide citation)

Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors a ...


8
John Michael Borkenhagen, Todd Alan Greenfield, James Anthony Marcella: Data strobe gating for source synchronous communications interface. International Business Machines Corporation, Wood Herron & Evans, September 6, 2005: US06940760 (31 worldwide citation)

A circuit arrangement and method are used in connection with a data latch that is coupled to a data source over a source synchronous communications interface to disable the data latch from latching data whenever the data source is not driving the source synchronous data strobe signal. As such, when ...


9
John Michael Borkenhagen, James Anthony Marcella: Programmable compensated delay for DDR SDRAM interface using programmable delay loop for reference calibration. International Business Machines Corporation, Joan Pennington, July 6, 2004: US06760856 (30 worldwide citation)

A programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface is provided. A programmable compensated delay apparatus includes a reference delay calibration circuit for providing a measured number of delay elements in one cycle. A programmab ...


10
Gerald Keith Bartley, John Michael Borkenhagen, Robert Allen Drehmel, James Anthony Marcella: Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes. International Business Machines Corporation, Wood Herron & Evans, August 7, 2007: US07254663 (27 worldwide citation)

A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many i ...