1
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John G Favor, Dale R Greenley, Robert A Cargnoni: Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags. Nexgen Microsystems, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226126 (369 worldwide citation)

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat ...


2
John G Favor, Korbin Van Dyke, David R Stiles: Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency. NexGen Microsystems, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226130 (260 worldwide citation)

The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch pre ...


3
John G Favor, Frederick D Weber: Flexible implementation of a system management mode (SMM) in a processor. Advanced Micro Devices, Ken Koestner, Skjerven Morrill MacPherson Franklin & Friel L, July 25, 2000: US06093213 (106 worldwide citation)

A system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is "soft" and freely defined. A system management ...


4
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John G Favor, Dale R Greenley, Robert A Cargnoni: Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts. NexGen, Townsend and Townsend Khourie and Crew, August 15, 1995: US05442757 (103 worldwide citation)

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat ...


5
Korbin S Van Dyke, David R Stiles, John G Favor: Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence. NexGen Microsystems, Townsend and Townsend Khourie and Crew, July 20, 1993: US05230068 (102 worldwide citation)

A system which integrates the multiple instruction queues and the branch target cache (BTC) of a high performance CPU design into a single physical structure. Effectively, the queues are merged into the BTC in such a manner that, at any point in time, most of this structure functions as a BTC while ...


6
David R Stiles, John G Favor, Korbin S Van Dyke: Two-level branch prediction cache. Nexgen Microsystems, Townsend and Townsend, November 10, 1992: US05163140 (100 worldwide citation)

An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited numbe ...


7
John S Thayer, John G Favor, Frederick D Weber: System and method for conditional moving an operand from a source register to destination register. Advanced Micro Devices, Compaq Computer Corporation, Robert C Kowert, Conley Rose & Tayon PC, October 2, 2001: US06298438 (79 worldwide citation)

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maxi ...


8
John G Favor, Amos Ben Meir: Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay. Advanced Micro Devices, David T Millers, Skjerven Morrill MacPherson Franklin & Friel, August 25, 1998: US05799165 (69 worldwide citation)

A superscalar microprocessor includes a scheduler which contains storage for information related to operations and scan logic for selecting operations for out-of-order execution by a set of execution units. To provide fast operation, the selection is made without regard for the availability of opera ...


9
John G Favor, Amos Ben Meir, Warren G Stapleton: Unified multi-function operation scheduler for out-of-order execution in a superscaler processor. Advanced Micro Devices, David Miller, Skjerven Morrill MacPherson, February 27, 2001: US06195744 (68 worldwide citation)

A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. The scheduler issues operations to execution ...


10
John S Thayer, John G Favor, Frederick D Weber: Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage. Compaq Computer, Advanced Micro Devices, Robert C Kowert, Kevin L Daffer, Conley Rose & Tayon P C, January 9, 2001: US06173366 (62 worldwide citation)

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maxi ...