1
John F Brown III, Shawn Persels, Jeanne Meyer: Branch prediction unit for high-performance processor. Digital Equipment Corporation, Arnold White & Durkee, February 28, 1995: US05394529 (109 worldwide citation)

A pipelined CPU executes instructions of variable length, and references memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A branch prediction ...


2
John F Brown III: Method for implementing synchronous pipeline exception recovery. Digital Equipment Corporation, Arnold White & Durkee, October 17, 1989: US04875160 (79 worldwide citation)

Pipelined CPUs achieve high-performance by fine tuning the pipe stages to execute typical instruction sequences. Atypical instruction sequences result in pipeline exceptions. The disclosed method provides graceful exception handling and recovery in a micropipelined memory interface. The use of a mem ...


3
Thomas B Brightman, Andrew T Brown, John F Brown, James A Farrell, Andrew D Funk, David J Husak, Edward J McLellan, Mark A Sankey, Paul Schmitt, Donald A Priore: Digital communications processor. Freescale Semiconductor, Gordon E Nelson, August 29, 2006: US07100020 (52 worldwide citation)

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). T ...


4
John F Brown III, G Michael Uhler, Richard L Sites: Computer system performance evaluation system and method. Digital Equipment Corporation, Diane C Drozenski, Denis G Maloney, Arthur W Fisher, September 12, 1995: US05450349 (49 worldwide citation)

A system for evaluating the performance of a computer system having a processor that passes through a plurality of processor states during operation and an associated system memory includes an operating unit for receiving a request to monitor specific process states from a user. Firmware causes the ...


5
John F Brown III, Mary K Gowan: Register conflict scoreboard in pipelined computer using pipelined reference counts. Digital Equipment Corporation, Diane C Drozenski, Denis G Maloney, Arthur W Fisher, January 30, 1996: US05488730 (40 worldwide citation)

A data dependency scoreboard for a pipelined digital computer includes a source counter and a destination counter for each general purpose register (GPR). The source counter for each GPR is incremented each time that a specifier is decoded that specifies the use of the source counter's GPR as a sour ...


6
John F Brown III, G Michael Uhler, William R Wheeler: Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory read. Compaq Computer Corporation, Conley Rose & Tayon P C, May 29, 2001: US06240508 (38 worldwide citation)

A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into ...


7
Douglas E Sanders, George M Uhler, John F Brown III: Pipelined digital CPU with deadlock resolution. Digital Equipment Corporation, Arnold White & Durkee, April 9, 1991: US05006980 (32 worldwide citation)

A pipelined CPU employs separate microinstruction pipelines for the execution unit and memory management unit. Deadlocks can occur in a pipelined CPU when there is data dependency in two consecutive instructions. The later instruction may stall the pipeline if operands fetched by an earlier instruct ...


8
John F Brown: Thick film resistor circuits. Bell Telephone Laboratories Incorporated, Lester H Birnbaum, February 20, 1979: US04140817 (30 worldwide citation)

Disclosed is a method and resulting product whereby thick film conductors which require a reducing firing atmosphere may be included in circuits with thick film resistors requiring an oxidizing firing atmosphere. In accordance with one embodiment, a fritless paste including copper is deposited onto ...


9
John F Brown, Robert M Stanton: Fabrication of bi-level circuits. Bell Telephone Laboratories Incorporated, Lester H Birnbaum, March 4, 1980: US04191789 (23 worldwide citation)

Disclosed is a method of fabricating bi-level circuits which include metallization of via holes (14 and 15) in insulating subustrates (10). A thick film metal paste (13) is prepared which according to one embodiment comprises copper, glass frit and an organic vehicle including a low molecular weight ...


10
John F Brown III, Mary K Gowan: Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Lindsay G McGuinness, September 12, 1995: US05450555 (20 worldwide citation)

A pipelined processor has an instruction unit for decoding instructions and pre-processing operands prior to instruction execution, and an execution unit for executing the decoded instructions. The pre-processing of operands includes changes to general purpose registers, and the changes are recorded ...