1
Lars Wolfgang Liebmann, Robert Thomas Sayah, John Edward Barth Jr: Fidelity enhancement of lithographic and reactive-ion-etched images by optical proximity correction. International Business Machines Corporation, H Daniel Schnurmann, April 14, 1998: US05740068 (194 worldwide citation)

A method for performing optical proximity correction is disclosed that not only limits the optical proximity correction to electrically relevant structures, but also improves the accuracy of the corrections by processing individual feature edges, and minimizes the mask manufacturing impacts by avoid ...


2
Howard Leo Kalter, John Edward Barth Jr, Jeffrey Harris Dreibelbis, Rex Ngo Kho, John Stuart Parenteau Jr, Donald Lawrence Wheater, Yotaro Mori: Processor based BIST for an embedded memory. International Business Machines Corporation, Charles W Peterson Jr, October 5, 1999: US05961653 (98 worldwide citation)

An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as bra ...


3
Darren L Anand, John Edward Barth Jr, John Atkinson Fifield, Pamela Sue Gillis, Peter O Jakobsen, Douglas Wayne Kemerer, David E Lackey, Steven Frederick Oakland, Michael Richard Ouellette, William Robert Tonti: Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox. International Business Machines Corporation, Richard A Henkler, Bracewell & Patterson L, June 10, 2003: US06577156 (61 worldwide citation)

A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of ...


4
Howard Leo Kalter, John Edward Barth Jr: Integrated circuit chip with a wide I/O memory array and redundant data lines. International Business Machines Corporation, H Daniel Schnurmann, Whitham Curtis & Whitham, August 18, 1998: US05796662 (22 worldwide citation)

An integrated circuit chip with RAM, a RAM macro or bit slice data logic and at least one spare array element or spare slice element and the redundancy scheme therefor. The chip includes a wide data path with a plurality of interchangeable elements such as bit slice elements or memory element and at ...


5
William Robert Reohr, John Edward Barth Jr, Toshiaki Kirihata, Derek H Leu, Donald W Plass: High voltage word line driver. International Business Machines Corporation, Preston J Young, Otterstedt Ellenbogen & Kammer, February 21, 2012: US08120968 (8 worldwide citation)

A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. ...


6
John Edward Barth Jr, Howard Leo Kalter: Boundary independent bit decode for a SDRAM. International Business Machines Corporation, Charles W Peterson Jr, H Daniel Schnurmann, September 2, 1997: US05663924 (8 worldwide citation)

A boundary independent decoder for a Synchronous Dynamic Random Access Memory (SDRAM) with an n bit burst transfer block length. A user, usually a processor or microprocessor requests access to a block of SDRAM memory. The requested block may begin between array decode boundaries. A column address i ...


7
John Edward Barth Jr, Kevin William Gorman: Structure for redundancy programming of a memory device. International Business Machines Corporation, Schmeiser Olsen & Watts, Michael J LeStrange, May 31, 2011: US07954028 (4 worldwide citation)

A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuits for implementing a method wherein it is assumed that all fails are row fails until determined to be bi ...


8
John Edward Barth Jr, Kerry Bernstein, Ethan Harrison Cannon, Francis Roger White: Deep trench capacitor for SOI CMOS devices for soft error immunity. International Business Machines Corporation, Cantor Colburn, Vazken Alexanian, August 2, 2011: US07989865 (3 worldwide citation)

A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, a ...


9
John Edward Barth Jr, Paul C Parries, William Robert Reohr, Matthew R Wordeman: Differential and hierarchical sensing for memory circuits. International business Machines Corporation, Ryan Mason & Lewis, June 3, 2008: US07382672 (3 worldwide citation)

A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias ...


10
John Edward Barth Jr, Paul Christian Parries, Norman Whitelaw Robson: Repair of address-specific leakage. International Business Machines Corporation, Infineon Technologies, Ira D Blecker, October 18, 2005: US06957372 (2 worldwide citation)

An integrated circuit having a DRAM array connected to a power supply is tested for excessive current draw by selectively applying voltage to a single wordline or bitline, measuring current drawn, comparing the result with a reference number representing acceptable leakage, and replacing columns of ...