1
Rakesh H Patel, John E Turner, Myron W Wong: Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements. Altera Corporation, Robert R Jackson, G Victor Treyz, December 6, 1994: US05371422 (225 worldwide citation)

A programmable logic device is provided that has a two-dimensional array of logic array blocks. The logic array blocks, which contain advanced macrocells, contain programmable input arrays based on pterm logic and are two-dimensionally interconnected with global horizontal and vertical conductors. T ...


2
John E Turner, David L Rutledge: Programmable logic device. Lattice Semiconductor Corporation, Roberts and Quiogue, August 2, 1988: US04761768 (158 worldwide citation)

An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed and erased by Fowler-Nordheim tunneling. T ...


3
Christopher J Pass, James D Sansbury, Raminda U Madurawe, John E Turner, Rakesh H Patel, Peter J Wright: Programmable interconnect junction. Altera Corporation, Townsend & Townsend and Crew, September 7, 1999: US05949710 (118 worldwide citation)

A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconne ...


4
John E Turner, David L Rutledge, Roy D Darling: In-system programmable logic device. Lattice Semiconductor Corporation, Marger & Johnson P C, November 7, 1989: US04879688 (114 worldwide citation)

An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed ...


5
John E Turner, Gregg R Josephson: Programmable logic array. Lattice Semiconductor Corporation, Roberts and Quiogue, August 23, 1988: US04766569 (84 worldwide citation)

A programmable logic array is disclosed employing arrays of electrically erasable and programmable cells. The device includes a dual purpose programming circuit which is employed to provide programming data to the AND array to program the AND array cells, and to provide OR array row selection data d ...


6
John E Turner, David L Rutledge, Roy D Darling: In-system programmable logic device with four dedicated terminals. Lattice Semiconductor Corporation, Marger & Johnson, August 8, 1989: US04855954 (68 worldwide citation)

An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retain a particular programmed l ...


7
John E Turner, David L Rutledge, Roy D Darling: Programmable logic device configurable input/output cell. Lattice Semiconductor Corporation, Marger & Johnson, January 23, 1990: US04896296 (57 worldwide citation)

An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed ...


8
John E Turner, Richard G Cliff: Complementary low power non-volatile reconfigurable EEcell. Altera Corporation, Jeffrey H Ingerman, Robert W Morris, December 21, 1993: US05272368 (56 worldwide citation)

A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. A CMOS inverter is formed by fabricating an n-channel MOSFET and a p-channel MOSFET with merged floating gate regions. A tunnel capacitor allows charge to be supplied to or removed from the floatin ...


9
Rakesh H Patel, John E Turner: Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions. Altera Corporation, Townsend and Townsend and Crew, August 5, 2003: US06604228 (55 worldwide citation)

A technique of fabricating an integrated circuit adaptable for use in various operating voltage environments. The same integrated circuit design may be used in different operating modes depending on the particular option selected. For example, there may be three options (


10
Rakesh H Patel, John E Turner, John D Lam, Wilson Wong: Circuitry for a low internal voltage integrated circuit. Altera Corporation, Townsend and Townsend and Crew, February 15, 2000: US06025737 (47 worldwide citation)

A technique and circuitry for interfacing an integrated circuit manufactured using technology compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, the integrated circuit is fabricated using technology compatible with an internal sup ...