1
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched. Townsend and Townsend and Crew, January 23, 1996: US05487156 (177 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


2
Michael A Malcolm, Mark L C Gerhold, Gary W Hodgman, Marshall M Parker, Lawrence D Rogers, John E Spracklen: Local area contention network data communication system. Burroughs Corporation, Mervyn L Young, Kevin R Peterson, May 25, 1982: US04332027 (122 worldwide citation)

This disclosure relates to a station for a data transmission network which is adapted to operate in a cyclic mode for contending for access to the network channel along with other stations of the network. The three states of the cycle are the idle state, the packet-being-transmitted state and the ac ...


3
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code. Hyundai Electronics America, Townsend and Townsend and Crew, April 29, 1997: US05625837 (120 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


4
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture supporting multiple speculative branching. Hyundai Electronics America, Townsend and Townsend and Crew, October 1, 1996: US05561776 (115 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


5
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture supporting multiple speculative branches and trap handling. Hyundai Electronics America, Townsend and Townsend and Crew, January 7, 1997: US05592636 (75 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


6
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing out-of-order execution. Hyundai Electronics America, Townsend and Townsend and Crew, May 6, 1997: US05627983 (74 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


7
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing speculative, out of order execution of instructions. Hyundai Electronics America, Pennie & Edmonds, January 13, 1998: US05708841 (70 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


8
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing speculative, out of order execution of instructions and trap handling. Hyundai Electronics America, Pennie & Edmonds, November 3, 1998: US05832293 (69 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


9
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture supporting speculative, out of order execution of instructions including multiple speculative branching. Hyundai Electronics America, Pennie & Edmonds, August 18, 1998: US05797025 (63 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


10
John E Spracklen, Mark L C Gerhold: Line driver circuit for a local area contention network. Burroughs Corporation, Mervyn L Young, Kevin R Peterson, June 29, 1982: US04337465 (47 worldwide citation)

This disclosure relates to a line driver circuit for a station in a data transmission network, which driver circuit is adapted to drive the channel medium with a constant current so that conflicts or collisions with data transmissions from other stations will be cancelled out thereby preventing any ...